PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 33

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8811_4
Product data sheet
11.2 I
of the acknowledge-related clock pulse (set-up and hold times must be taken into
consideration). A master receiver must signal an end-of-data to the transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to enable the master to generate a
STOP condition.
The PCF8811 is a slave receiver/transmitter. If data is to be read from the device, the
SDAH pad must be connected, otherwise the SDAH pad is unused.
Hs-mode can only commence after the following conditions:
The master code has two functions: it allows arbitration and synchronization between
competing masters at F/S-mode speeds, resulting in one winner. The master code also
indicates the beginning of an Hs-mode transfer. These conditions are shown in
and
2
Fig 28. Acknowledge on the I
Fig 29. Data transfer format in Hs-mode
•
•
•
C-bus Hs-mode protocol
START condition (S)
8-bit master code (0000 1xxx)
Not-acknowledge bit (A)
Figure
S
by transmitter
data output
by receiver
data output
SCL from
MASTER CODE
30.
master
F/S-mode
condition
START
S
Rev. 04 — 27 June 2008
A
Sr SLAVE ADD.
2
C-bus
Hs-mode (current-source for SCLH enabled)
1
R/W
2
A
(n bytes + ack.)
80 x 128 pixels matrix LCD driver
DATA
not acknowledge
acknowledge
8
A/A
acknowledgement
clock pulse for
PCF8811
Sr SLAVE ADD.
P
© NXP B.V. 2008. All rights reserved.
Hs-mode continues
9
F/S-mode
mbc602
msc616
Figure 29
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