MAX5037 MAXIM [Maxim Integrated Products], MAX5037 Datasheet - Page 10

• Manufacturer Part Number: MAX5037
• Description: VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

VRM 9.0, Dual-Phase, Parallelable,
Average Current-Mode Controller
10
24, 31
25, 30
PIN
______________________________________________________________________________________
26
27
28
29
36
38
41
42
DL1, DL2
LX1, LX2
CLKOUT
PLLCMP
PHASE
NAME
CLKIN
PGND
V
V
IN
DD
CC
Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal
for the high-side driver.
Low-Side Gate-Driver Output. Synchronous MOSFET gate drivers for the two phases.
Supply Voltage for Low-Side and High-Side Drivers. V
of 0.1µF and 1µF ceramic capacitors to PGND and a 1 resistor to V
currents of the driver from the internal circuitry.
Internal 5V Regulator Output. V
and 0.1µF ceramic capacitors.
Supply Voltage Connection. Connect IN to V
Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and V
returns together.
Oscillator Output. CLKOUT is phase shifted from CLKIN by the amount specified by PHASE. Use
CLKOUT to parallel additional MAX5037s.
CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and
600kHz. The PWM frequency defaults to the internal oscillator if CLKIN is connected to V
Connect CLKIN to SGND to set the internal oscillator to 250kHz or connect to V
oscillator to 500kHz. CLKIN has an internal 5µA pulldown current.
Phase Shift Setting Input. Drive PHASE high for 120°, leave PHASE unconnected for 90°, and force
PHASE low for 60° of phase shift between the rising edges of CLKOUT and CLKIN/DH1.
External Loop-Compensation Input. Connect compensation network for the phase-locked loop (see
Phase-Locked Loop section).
CC
is derived internally from the IN voltage. Bypass to SGND with 4.7µF
CC
FUNCTION
for a 5V system.
Pin Description (continued)
CC
powers V
DD
CC
. Connect a parallel combination
to filter out the high peak
CC
DD
to set the internal
bypass capacitor
CC
or SGND.