MAX5037 MAXIM [Maxim Integrated Products], MAX5037 Datasheet - Page 18

• Manufacturer Part Number: MAX5037
• Description: VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

Applying the voltage-positioning window at different
VRM voltage settings requires that R
age on REG internally regulates to the programmed
VID output voltage. Choose R
REG to 50µA. For example, for a VID setting of 1.85V,
calculate the minimum allowed R
1.85V/50µA = 37kΩ. To use larger values of R
maintaining the required gain of the VEA, use larger
values for R
In the case of a VID voltage setting equal to V
at I
tion (Figure 7). For systems requiring V
absolute maximum voltage when I
calculate R
The DAC programs the output voltage. The DAC typi-
cally receives a digital code, alternatively, the VID
inputs are hard-wired to SGND or left open-circuit.
VID0–VID4 logic can be changed while the MAX5037 is
active, initiating a transition to a new output voltage
level. Change VID0–VID4 together, avoiding greater
than 1µs skew between bits. Otherwise, incorrect DAC
readings may cause a partial transition to the wrong
voltage level followed by the intended transition to the
correct voltage level, lengthening the overall transition
time. For any low-going VID step of 100mV or more, the
OVP can trip simply because the OVP trip reference
changes instantaneously with the VID code, but the
converter output does not follow immediately. The con-
verter output drops at a rate depending on the output
capacitor, inductor load, and the closed-loop band-
width of the converter. Do not exceed a maximum VID
step size of 75mV.
VRM 9.0, Dual-Phase, Parallelable,
Average Current-Mode Controller
Figure 7. Limiting the Voltage-Positioning Window
18
V
V
COREMAX
COREMAX
OUT
V
COREMAX
______________________________________________________________________________________
- ∆V
- ∆V
= 0 (no load), R
R
REG
≤ VID
OUT
OUT
REG
IN
/2
/2
NO LOAD
.
=
using following the equation:
R
IN
+
R
CNTR
F
R
DAC Inputs (VID0–VID4)



IN
1
−
×
1/2 LOAD
LOAD (A)
= ∞ from the above equa-
V
REG
COREMAX
R
F
VID
to limit the current at
OUT
REG
REG
COREMAX



= 0 (no load),
= R
as R
F
FULL LOAD
. The volt-
REG
COREMAX
REG
as an
while
(6)
=
The available DAC codes and resulting output voltages
(Table 1) comply with Intel’s VRM 9.0 specification.
Internal pullup resistors connect the VID inputs to a
nominal internal 3V supply. Force the VID inputs below
0.8V for logic low or leave unconnected for logic high.
Output voltage accuracy with respect to the pro-
grammed VID voltage is ±0.8% over the -40°C to +85°C
temperature range.
Table 1. Output Voltage vs. DAC Codes
VID4
VID INPUTS (0 = CONNECTED TO
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SGND, 1 = OPEN CIRCUIT)
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VOLTAGE (V)
Output Off
OUTPUT
V
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
1.800
1.825
1.850
OUT