MAX5037 MAXIM [Maxim Integrated Products], MAX5037 Datasheet - Page 20

• Manufacturer Part Number: MAX5037
• Description: VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

The PGOOD output is high if all of the following condi-
tions are met (Figure 9):
1) The output is within 90% to 108% of the pro-
2) Both phases are providing current.
3) EN is HIGH.
A window comparator compares the differential amplifi-
er output (DIFF) against 1.08 times the programmed
VID output voltage for overvoltage and 0.90 times the
programmed VID output voltage for undervoltage moni-
toring. The phase failure comparator detects a phase
failure by comparing the current-error amplifier output
(CLP_) with a 2.0V reference.
Use a 10kΩ pullup resistor from PGOOD to a voltage
source less than or equal to V
outside the comparator window or a phase failure con-
dition forces the open-drain output low. The open-drain
MOSFET sinks 4mA of current while maintaining less
than 0.2V at the PGOOD output.
Output current contributions from the two phases are
within ±10% of each other. Proper current sharing
reduces the necessity to overcompensate the external
components. However, an undetected failure of one
phase driver causes the other phase driver to run con-
tinuously as it tries to provide the entire current require-
ment to the load. Eventually, the stressed operational
phase driver fails.
During normal operating conditions, the voltage level
on CLP_ is within the peak-to-peak voltage levels of the
PWM ramp. If one of the phases fails, the control loop
raises the CLP_ voltage above its operating range. To
determine a phase failure, the phase failure detection
circuit (Figure 9) monitors the output of the current
amplifiers (CLP1 and CLP2) and compares them to a
2.0V reference. If the voltage levels on CLP1 or CLP2
are above the reference level for more than 1250 clock
cycles, the phase failure circuit forces PGOOD low.
Average current-mode control has the ability to limit the
average current sourced by the converter during a fault
condition. When a fault condition occurs, the VEA out-
put clamps to 0.9V with respect to the common-mode
voltage (V
of the current-sense amplifiers (CA1 and CA2) (see
Figure 3). The current-sense amplifier’s gain of 18 limits
the maximum current in the inductor or sense resistor to
I
VRM 9.0, Dual-Phase, Parallelable,
Average Current-Mode Controller
20
LIMIT
grammed output voltage.
______________________________________________________________________________________
= 50mV/R
CM
= 0.6V) and is compared with the output
S
.
Power-Good Generator (PGOOD)
Overload Conditions
Phase Failure Detector
CC
. An output voltage
For applications requiring large output current, parallel
up to three MAX5037s (six phases) to triple the available
output current. The paralleled converters operating at the
same switching frequency but different phases keep the
capacitor ripple RMS currents to a minimum. Three par-
allel MAX5037 converters deliver up to 180A of output
current. To set the phase shift of the on-board PLL, leave
PHASE unconnected for 90° of phase shift (2 paralleled
converters), or connect PHASE to SGND for 60° of phase
shift (3 converters in parallel). Designate one converter
as master and the remaining converters as slaves.
Connect the master and slave controllers in a daisy-
chain configuration as shown in Figure 10. Connect
CLKOUT from the master controller to CLKIN of the first
slaved controller, and CLKOUT from the first slaved con-
troller to CLKIN of the second slaved controller. Choose
the appropriate phase shift for minimum ripple currents
at the input and output capacitors. The master controller
senses the output differential voltage through SENSE+
and SENSE- and generates the DIFF voltage. Disable the
voltage sensing of the slaved controllers by leaving DIFF
unconnected (floating). Figure 11 shows a detailed typi-
cal parallel application circuit using two MAX5037s. This
circuit provides four phases at an input voltage of 12V
and an output voltage range of 1.1V to 1.85V at 104A.
Figure 9. Power-Good Generator
DIFF
DAC_OUT
CLP1
CLP2
10% OF DAC
8% OF DAC
+2.0V
PHASE FAILURE DETECTION
Parallel Operation
PGOOD