MAX5037 MAXIM [Maxim Integrated Products], MAX5037 Datasheet - Page 14

• Manufacturer Part Number: MAX5037
• Description: VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

The MAX5037 accepts a wide input voltage range of
+4.75V to +5.5V or +8V to +28V. All internal control cir-
cuitry operates from an internally regulated nominal volt-
age of 5V. For input voltages of +8V or greater, the
internal V
The V
up to 80mA. Bypass V
low-ESR ceramic capacitors for high-frequency noise
rejection and stable operation (Figure 1).
V
nally from V
low-side MOSFET drivers. V
to the power source of the low-side MOSFET drivers.
Use V
power to the high-side MOSFET drivers. Connect the
V
ter. Use a 1Ω (R3) resistor and a parallel combination of
1µF and 0.1µF ceramic capacitors to filter out the high
peak currents of the MOSFET drivers from the sensitive
internal circuitry.
Calculate power dissipation in the MAX5037 as a prod-
uct of the input voltage and the total V
put current (I
and gate drive current (I
where, Q
charge of the low-side and high-side external
MOSFETs, I
quency of each individual phase.
For applications utilizing a +5V input voltage, disable
the V
The MAX5037 includes an undervoltage lockout with
hysteresis and a power-on reset circuit for converter
turn-on and monotonic rise of the output voltage. The
UVLO circuit monitors the V
actively holding down the power-good (PGOOD) out-
put. The UVLO threshold is internally set between
+4.0V and +4.5V with a 200mV hysteresis. Hysteresis
at UVLO eliminates “chattering” during startup.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches +4V. The
MAX5037 draws up to 4mA of current before the input
voltage reaches the UVLO threshold. The power-on reset
clears the overvoltage protection (OVP) fault latch at the
UVLO threshold to avoid unintentional OVP latching.
VRM 9.0, Dual-Phase, Parallelable,
Average Current-Mode Controller
14
CC
CC
regulator output to V
______________________________________________________________________________________
powers all internal circuitry. V
CC
CC
I
DD
CC
regulator by connecting IN and V
CC
output voltage regulates to 5V while sourcing
G1
= I
to charge the boost capacitors that provide
CC
Q
, Q
Q
regulator steps the voltage down to +5V.
Power-On Reset (POR)/Soft-Start
CC
is 4mA (typ), and f
+ f
and provides power to the high-side and
G2
Undervoltage Lockout (UVLO)/
). I
SW
, Q
CC
P
x (Q
D
CC
G3,
includes quiescent current (I
= V
DD
DD
G1
to SGND with 4.7µF and 0.1µF
and Q
):
IN
+ Q
through an R-C lowpass fil-
DD
CC
x I
CC
G2
V
is internally connected
SW
regulator output while
G4
IN
DD
+ Q
is the switching fre-
, V
are the total gate
CC
is derived exter-
G3
CC,
CC
regulator out-
+ Q
and V
together.
G4
)
(1)
(2)
DD
Q
)
The compensation network at the current-error amplifi-
er, CLP1 and CLP2, provides an inherent soft-start to
the VRM power supply. It includes a parallel combina-
tion of capacitors (C34, C36) and resistors (R5, R6) in
series with other capacitors (C33, C35) (see Figure 1).
The voltage at CLP_ limits the maximum current avail-
able to charge output capacitors. The capacitor on
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
The internal oscillator generates the 180° out-of-phase
clock signals required by the pulse-width modulation
(PWM) circuits. The oscillator also generates the 2V
voltage ramp signals necessary for the PWM compara-
tors. Connect CLKIN to SGND to set the internal oscillator
frequency to 250kHz or connect CLKIN to V
internal oscillator to 500kHz.
CLKIN is a CMOS logic clock for the phase-locked loop
(PLL). When driven externally, the internal oscillator
locks to the signal at CLKIN. A rising edge at CLKIN
starts the ON cycle of the PWM. Ensure that the exter-
nal clock pulse width is at least 200ns. CLKOUT pro-
vides a phase-shifted output with respect to the rising
edge of the signal at CLKIN. PHASE sets the amount of
phase shift at CLKOUT. Connect PHASE to V
120° of phase shift, leave PHASE unconnected for 90°
of phase shift, or connect PHASE to SGND for 60° of
phase shift with respect to CLKIN.
The MAX5037 requires compensation on PLLCMP even
when operating from the internal oscillator. The device
requires an active phase-locked loop in order to gener-
ate the proper clock signal required for PWM operation.
The MAX5037 uses an average current-mode control
scheme to regulate the output voltage (Figure 3). The
main control loop consists of an inner current loop and
an outer voltage loop. The inner loop controls the out-
put currents (I
loop controls the output voltage. The inner current loop
absorbs the inductor pole reducing the order of the
outer voltage loop to that of a single-pole system.
PHASE1
and I
PHASE2
Internal Oscillator
), while the outer
Control Loop
CC
to set the
CC
P-P
for