MAX5037 MAXIM [Maxim Integrated Products], MAX5037 Datasheet - Page 19

• Manufacturer Part Number: MAX5037
• Description: VRM 9.0, Dual-Phase, Parallelable, Average Current-Mode Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

The phase-locked loop (PLL) synchronizes the internal
oscillator to the external frequency source when driving
CLKIN. Connecting CLKIN to V
PWM frequency to default to the internal oscillator fre-
quency of 500kHz or 250kHz, respectively. The PLL
uses a conventional architecture consisting of a phase
detector and a charge pump capable of providing
20µA of output current. Connect an external series
combination capacitor (C31) and resistor (R4) and a
parallel capacitor (C32) from PLLCMP to SGND to pro-
vide frequency compensation for the PLL (Figure 1).
The pole-zero pair compensation provides a zero at f
= 1 / [R4 x (C31 + C32)] and a pole at f
C32). Use the following typical values for compensating
the PLL: R4 = 7.5kΩ, C31 = 4.7nF, C32 = 470pF. When
changing the PLL frequency, expect a finite locking
time of approximately 200µs.
The MAX5037 requires compensation on PLLCMP even
when operating from the internal oscillator. The device
requires an active-phase-locked loop in order to generate
the proper internally shifted clock available at CLKOUT.
The high-side (DH_) and low-side (DL_) drivers drive
the gates of external N-channel MOSFETs (Figure 1).
The drivers’ high-peak sink and source current capabil-
ity provides ample drive for the fast rise and fall times
of the switching MOSFETs. Faster rise and fall times
result in reduced cross-conduction losses. For modern
CPU applications where the duty cycle is less than
50%, choose high-side MOSFETs (Q1 and Q3) with a
moderate R
low-side MOSFETs (Q2 and Q4) with very low R
and moderate gate charge.
The driver block also includes a logic circuit that pro-
vides an adaptive non-overlap time to prevent shoot-
through currents during transition. The typical
non-overlap time is 60ns between the high-side and
low-side MOSFETs.
V
The high-side drivers derive their power through a
bootstrap capacitor and V
to the low-side drivers. Connect a 0.47µF low-ESR
ceramic capacitor between BST_ and LX_. Bypass V
to PGND with 1µF and 0.1µF low-ESR ceramic capaci-
tors. Reduce the PC board area formed by these
capacitors, the rectifier diodes between V
boost capacitor, the MAX5037, and the switching
MOSFETs.
DD
powers the low- and high-side MOSFET drivers.
Phase-Locked Loop: Operation and
DS(ON)
MOSFET Gate Drivers (DH_, DL_)
______________________________________________________________________________________
and very low gate charge. Choose
DD
supplies power internally
CC
VRM 9.0, Dual-Phase, Parallelable,
or SGND forces the
Average Current-Mode Controller
Compensation
P
DD
= 1 / (R4 x
and the
DS(ON)
BST_
DD
Z
The MAX5037 includes output overvoltage protection
(OVP), undervoltage protection (UVP), phase failure,
and overload protection to prevent damage to the pow-
ered electronic circuits.
The OVP comparator compares the OVPIN input to the
overvoltage threshold. The overvoltage threshold is typ-
ically +13% above the programmed VID output voltage.
A detected overvoltage event latches the comparator
output forcing the power stage into the OVP state. In
the OVP state, the high-side MOSFETs turn off and the
low-side MOSFETs latch on. Use the OVPOUT high-
current-output driver to turn on an external crowbar
SCR. When the crowbar SCR turns on, a fuse must
blow or the source current for the MAX5037 regulator
must be limited to prevent further damage to the exter-
nal circuitry. Connect the SCR close to the input source
and after the fuse. Use an SCR large enough to handle
the peak I
tors discharging and the current sourced by the power
source output. Connect DIFF to OVPIN for differential
output sensing and overvoltage protection. Add an RC
delay to reduce the sensitivity of overvoltage circuit and
avoid nuisance tripping of the converter (Figure 8).
For any low-going VID step of 75mV or more, the OVP
can trip because the OVP trip reference changes instan-
taneously with the VID code, but the converter output
does not follow immediately. The converter output drops
at a rate depending on the output capacitor, inductor
load, and the closed-loop bandwidth of the converter.
Figure 8. OVP Input Delay
2
t energy due to the input and output capaci-
MAX5037
Overvoltage Protection (OVP)
EAOUT
OVPIN
DIFF
EAN
Protection
1kΩ
R
F
0.1µF
R
IN
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