PCA9665D NXP [NXP Semiconductors], PCA9665D Datasheet - Page 17

• Manufacturer Part Number: PCA9665D
• Description: Fm+ parallel bus to I2C-bus controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA9665_3
Product data sheet
8.3.1 Master Transmitter Byte mode
8.3 Byte mode
P — STOP condition
In
circles are used to indicate when the serial interrupt flag is set. A serial interrupt is not
generated when I2CSTA = F8h. This happens on a STOP condition or when an external
reset is generated (at power-up, when RESET pin is going LOW or during a software reset
on the parallel bus). The numbers in the circles show the status code held in the I2CSTA
register. At these points, a service routine must be executed to continue or complete the
serial transfer. These service routines are not critical since the serial transfer is
suspended until the serial interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in I2CSTA is used to branch to
the appropriate service routine. For each status code, the required software action and
details of the following serial transfer are given in
Table
In the Master Transmitter Byte mode, a number of data bytes are transmitted to a slave
receiver (see
I2CCON must be initialized as shown in
Table 26.
ENSIO must be set to logic 1 to enable the PCA9665. If the AA bit is reset, the PCA9665
will not acknowledge its own slave address in the event of another device becoming
master of the bus. (In other words, if AA is reset, PCA9665 cannot enter a slave mode.)
STA, STO, and SI must be reset. Once ENSIO has been set to 1, it takes about 550 s for
the oscillator to start up.
The Master Transmitter Byte mode may now be entered by setting the STA bit. The
I
as the bus becomes free. When a START condition is transmitted, the serial interrupt flag
(SI) is set, the Interrupt line (INT) goes LOW and the status code in the status register
(I2CSTA) will be 08h. This status code must be used to vector to an interrupt service
routine that loads I2CDAT with the slave address and the data direction bit (SLA+W). A
write to I2CCON resets the SI bit, clears the Interrupt (INT goes HIGH) and allows the
serial transfer to continue.
When the slave address with the direction bit have been transmitted, the Serial Interrupt
flag (SI) is set again, the Interrupt line (INT) goes LOW again and I2CSTA is loaded with
the following possible codes:
Bit
Symbol
Value
2
C-bus state machine will first test the I
•
•
•
Figure
18h if an acknowledgment bit (ACK) has been received
20h if an no acknowledgment bit (NACK) has been received
38h if the PCA9665 lost the arbitration
35,
7,
Table
I2CCON initialization (Byte mode)
Figure
Figure
AA
36,
X
7
8,
Table
7). Before the Master Transmitter Byte mode can be entered,
Figure
Rev. 03 — 12 August 2008
ENSIO
40, and
6
1
9,
Figure
Table
STA
5
0
10,
41.
2
Table
C-bus and generate a START condition as soon
Figure
STO
4
0
26.
11,
Fm+ parallel bus to I
Table
Figure
SI
3
0
27,
Table
12,
reserved reserved
Figure 13
X
2
28,
Table
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
and
X
1
31,
Figure
Table
MODE
17 of 90
0
0
32,
14,