PCA9665D NXP [NXP Semiconductors], PCA9665D Datasheet - Page 62

• Manufacturer Part Number: PCA9665D
• Description: Fm+ parallel bus to I2C-bus controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA9665_3
Product data sheet
Fig 20. Bus timing diagram; Unbuffered Master Transmitter mode
Master PCA9665 writes data to slave transmitter.
SDA
condition
SCL
INT
START
from slave receiver
8.12 I
7-bit address
The diagrams
PCA9665 in master/slave functions.
2
Fig 19. Schematic to power-on/power-off PCA9665
C-bus timing diagrams, Unbuffered mode
R/W = 0
LOW: V
DD
ACK
= ON
(Figure 20
interrupt
input control signal
HIGH: V
Rev. 03 — 12 August 2008
DD
through
first byte
= OFF
V
DD(3V3)
Figure
ACK
10 k
interrupt
1A
1OE
2A
2OE
23) illustrate typical timing diagrams for the
74LVC2G125
Fm+ parallel bus to I
n byte
100 pF
ACK
1Y
2Y
interrupt
PCA9665
© NXP B.V. 2008. All rights reserved.
2
002aab031
STOP
condition
C-bus controller
PCA9665
V
DD
20
002aac920
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