PCA9665D NXP [NXP Semiconductors], PCA9665D Datasheet - Page 19

• Manufacturer Part Number: PCA9665D
• Description: Fm+ parallel bus to I2C-bus controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA9665_3
Product data sheet
Fig 7.
(1) See
(2) Defined state when a single byte is sent and an ACK is received.
(3) Defined state when a single byte is sent and a NACK is received.
(4) Master Receiver Byte mode is entered when MODE = 0. Master Receiver Buffered mode is entered when MODE = 1.
Format and states in the Master Transmitter Byte mode (MODE = 0)
successful
transmission
to a Slave Receiver
next transfer started with a
repeated START condition
Not Acknowledge received after
the slave address
Not Acknowledge received after
a data byte
arbitration lost in slave address
or data byte
arbitration lost and addressed as slave
Table 27
DATA
from master to slave
from slave to master
08h
A
n
S
any number of data bytes and
their associated Acknowledge bits
This number (contained in I2CSTA) corresponds
to a defined state of the I
SLA
W
Rev. 03 — 12 August 2008
MT
A or A
B0h
D8h
18h
20h
38h
68h
2
A
A
A
C-bus.
(1)
other MST
continues
other MST
continues
F8h
P
to corresponding states in Slave Transmitter mode
to corresponding states in Slave Receiver mode
to corresponding states in Slave Receiver mode (General Call)
DATA
Fm+ parallel bus to I
A or A
28h
30h
38h
(2)
(3)
A
A
other MST
continues
F8h
10h
F8h
P
S
P
mode entry = MR
to Master Receiver
SLA
PCA9665
© NXP B.V. 2008. All rights reserved.
2
C-bus controller
002aab024
W
R
(4)
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