PCA9665D NXP [NXP Semiconductors], PCA9665D Datasheet - Page 63

• Manufacturer Part Number: PCA9665D
• Description: Fm+ parallel bus to I2C-bus controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA9665_3
Product data sheet
Fig 21. Bus timing diagram; Unbuffered Master Receiver mode
Fig 22. Bus timing diagram; Unbuffered Slave Transmitter mode
Fig 23. Bus timing diagram; Unbuffered Slave Receiver mode
(1) As defined in I2CADR register.
(1) As defined in I2CADR register.
SDA
condition
SCL
Master PCA9665 reads data from slave transmitter.
External master receiver reads data from PCA9665.
INT
Slave PCA9665 is written to by external master transmitter.
START
SDA
condition
SDA
condition
SCL
SCL
INT
INT
START
START
from slave PCA9665
from slave PCA9665
7-bit address
7-bit address
7-bit address
R/W = 0
R/W = 1
from slave
R/W = 1
(1)
(1)
ACK
ACK
ACK
interrupt
interrupt
interrupt
Rev. 03 — 12 August 2008
first byte
first byte
first byte
ACK
ACK
ACK
interrupt
interrupt
interrupt
from master receiver
from master receiver
n byte
Fm+ parallel bus to I
n byte
n byte
ACK
no ACK
no ACK
interrupt
interrupt
PCA9665
STOP
condition
© NXP B.V. 2008. All rights reserved.
2
002aab032
002aab033
(after STOP)
STOP
condition
STOP
condition
C-bus controller
002aab034
interrupt
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