PCA9665D NXP [NXP Semiconductors], PCA9665D Datasheet - Page 64

• Manufacturer Part Number: PCA9665D
• Description: Fm+ parallel bus to I2C-bus controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA9665_3
Product data sheet
Fig 24. Bus timing diagram; Buffered Master Transmitter mode
Fig 25. Bus timing diagram; Buffered Master Receiver mode
(1) 7-bit address + R/W = 0 byte and number of bytes sent = value programmed in I2CCOUNT register (BC[6:0]
(1) Number of bytes received = value programmed in I2CCOUNT register (BC[6:0]
Master PCA9665 writes data to slave transmitter.
Master PCA9665 reads data from slave transmitter.
SDA
condition
SDA
condition
SCL
SCL
INT
INT
START
START
from slave receiver
8.13 I
7-bit address
7-bit address
The diagrams
PCA9665 in master/slave functions.
2
C-bus timing diagrams, Buffered mode
R/W = 0
R/W = 1
from slave
(1)
ACK
ACK
(Figure 24
Rev. 03 — 12 August 2008
through
first byte
first byte
(1)
(1)
Figure
ACK
ACK
from master receiver
27) illustrate typical timing diagrams for the
n byte
n byte
Fm+ parallel bus to I
68).
(1)
(1)
no ACK
ACK
interrupt
PCA9665
© NXP B.V. 2008. All rights reserved.
2
002aab267
002aab268
STOP
condition
STOP
condition
C-bus controller
68).
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