DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 19

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
10.2.6 Frame assembly
DAC1408D650 supports only /F/ = 1, which means that every frame clock period carries
one byte per lane.
Frame assembly combines the octet of lane_0 with the 6 msb bits of lane_1 and
re-assemble the original 14 bits sample. The same is done for lane_2 and lane_3. Tail bits
are dropped.
The frame assembler also handles error previously triggered.
If scrambling is enabled:
If scrambling is disabled:
If a nit_err (not in table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous sample (14 bits) will be repeated 2 times for I
(lane_0, lane_1). The same is done for : Q (lane_2, lane_3).
if a nit_err (not in table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous sample (14 bits) will be repeated once for I (lane_0,
lane_1). The same is done for : Q (lane_2, lane_3).
Rev. 01 — 26 May 2009
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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