DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 48

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Table 60.
Default settings are shown highlighted.
Table 61.
Bit
6 to 4
3 to 2
1 to 0
Bit
4
3
2
1 to 0
Symbol
DSP-SEL[2:0]
DLP_SEL[1:0]
LN_SEL[1:0]
Symbol
SEL_RI
SEL_FD
SEL_AD
SEL_CK[1:0]
IO_MUX_CNTRL0 register (address 1Bh) bit description
IO_MUX_CNTRL1 register (address 1Ch) bit description
Rev. 01 — 26 May 2009
Access Value
R/W
R/W
R/W
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value
R/W
R/W
R/W
R/W
000
001
010
011
100
101
00
01
10
11
00
01
10
11
Description
0
1
0
1
0
1
00
01
10
11
MX_DCLK <= EN_DATA_I_CDI and
DATA_I_CDI_0
MX_DCLK <= EN_DATA_I_CDI and
DATA_I_CDI_1OFF
MX_DCLK <= EN_DATA_Q_CDI and
DATA_Q_CDI_0
MX_DCLK <= EN_DATA_Q_CDI and
DATA_Q_CDI_1
MX_DCLK <= I_EN and
I_OUT(INVSINC_I_OUT) and "00"
MX_DCLK <= Q_EN and
Q_OUT(INVSINC_Q_OUT) and "00" others:
MX_DCLK <= "101010101010101"
MX_FCLK <= EN_DATA_I_DLP and
DATA_I_DLP
MX_FCLK <= EN_DATA_Q_DLP and
DATA_Q_DLP
MX_FCLK <= MON_DBG_BUS
MX_FCLK <= "010101010101010"
MX_A/MX_F10 <= DATA_LN0 / F10_LN0
MX_A/MX_F10 <= DATA_LN1 / F10_LN1
MX_A/MX_F10 <= DATA_LN2 / F10_LN2
MX_A/MX_F10 <= DATA_LN3 / F10_LN3
Description
RO_INTR <= INTR
RO_INTR <= RINGOSCILLATOR
MX_D <= MX_FCLK
MX_D <= MX_DCLK
IO[14:0] <= "00000" & MX_A
IO[14:0] <= MX_D
IO[15 ] <= RO_INTR
IO[15] <= MX_F10
IO[15] <= FCLK
IO[15] <= DCLK
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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