DAC1408D650HW/C1 NXP [NXP Semiconductors], DAC1408D650HW/C1 Datasheet - Page 55

• Manufacturer Part Number: DAC1408D650HW/C1
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Table 73.
Table 74.
Table 75.
Table 76.
Bit
7
6 to 5 SEL_ILA[1:0]
4 to 2 SEL_LOCK[2:0]
1
0
Bit Symbol
1
0
Bit
7 to 4 MAN_ALIGN_LN1[3:0] R/W
3 to 0 MAN_ALIGN_LN0[3:0] R/W
Bit
7 to 4 MAN_ALIGN_LN3[3:0] R/W
3 to 0 MAN_ALIGN_LN2[3:0] R/W
DYN_ALIGN_ENA
FORCE_ALIGN
Symbol
SEL_421_211
SUP_LANE_SYN
EN_SCR
Symbol
Symbol
ILA_CNTRL register (address 07h) bit description
FORCE_ALIGN register (address 08h) bit description
MAN_ALIGN_LN_0_1 register (address 09h) bit description
MAN_ALIGN_LN_0_1 register (address 0Ah) bit description
Rev. 01 — 26 May 2009
Access Value Description
R/W
R/W
Access Value
R/W
R/W
R/W
R/W
R/W
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access Value Description
Access Value Description
20h
0
1
20h
0
1
0
1
00
01
10
11
000
001
010
011
100
101
0
1
0
1
32h
32h
32h
32h
Description
no dynamic re-alignment
dynamic re-alignment (and monitoring) enabled
automatic lane alignment based on /A/-symbols
manual lane alignment based on man_align_lnx
indicates alignment data-delay for lane_1 [ 1..15]
indicates alignment data-delay for lane_0 [ 1..15]
inter-lane alignment based on ln3:ln2 and/or
ln1:ln0
inter-lane alignment based on ln3:ln0
ila is done after receiving 1 /A/-symbol
ila is done after receiving 2 /A/-symbols
ila is done after receiving 3 /A/-symbols
ila is done after receiving 4 /A/-symbols
ila may start only if all (4 or 2) lanes are locked
ila may start if one of the (4 or 2) lanes are locked
ila may start if lane_0 is locked
ila may start if lane_1 is locked
ila may start if lane_2 is locked
ila may start if lane_3 is locked
inter lane alignment synchronization disabled
inter lane alignment synchronization enabled
data descrambling disabled
scrambling ln0 depends on data descrambling
enabled
indicates alignment data-delay for lane_3 [ 1..15]
indicates alignment data-delay for lane_2 [ 1..15]
DAC1408D650
© NXP B.V. 2009. All rights reserved.
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