ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 17

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

PIN DESCRIPTIONS
ADSP-BF531/ADSP-BF532 processor pin definitions are listed
in
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
Table 9. Pin Descriptions
Pin Name
Memory Interface
Asynchronous Memory Control
Synchronous Memory Control
Timers
Table
ADDR19–1
DATA15–0
ABE1–0/SDQM1–0
BR
BG
BGH
AMS3–0
ARDY
AOE
ARE
AWE
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
TMR0
TMR1/PPI_FS1
TMR2/PPI_FS2
9.
O
Type Function
I/O
O
I
O
O
O
I
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
Address Bus for Async/Sync Access
Data Bus for Async/Sync Access
Byte Enables/Data Masks for Async/Sync Access A
Bus Request
Bus Grant
Bus Grant Hang
Bank Select
Hardware Ready Control
Output Enable
Read Enable
Write Enable
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output
A10 Pin
Bank Select
Timer 0
Timer 1/PPI Frame Sync1
Timer 2/PPI Frame Sync2
Rev. D | Page 17 of 60 | August 2006
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs as noted
in the table footnotes.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Driver
Type
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
C
C
C
ADSP-BF531/ADSP-BF532
1
Pull-Up/Down Requirement
None
None
None
Pull-up Required If Function Not Used
None
None
None
Pull-up Required If Function Not Used
None
None
None
None
None
None
None
None
None
None
None
None
None