ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 45

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

POWER DISSIPATION
Many operating conditions can affect power dissipation. System
designers should refer to EE-229: Estimating Power for
ADSP-BF531/ADSP-BF532/ADSP-BF533 Blackfin Processors on
the Analog Devices website (www.analog.com)—use site search
on “EE-229.” This document provides detailed information for
optimizing your design for lowest power.
See the ADSP-BF53x Blackfin Processor Hardware Reference
Manual for definitions of the various operating modes and for
instructions on how to minimize system power.
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section.
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point V
V
V
Output Enable Time Measurement
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time t
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure
The time t
nal switches, to when the output voltage reaches V
V
and V
V
interval from when the output starts driving to when the output
reaches the V
Time t
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t
difference between t
side of
DDEXT
DDEXT
TRIP
TRIP
(low). For V
(high) is 2.0 V and V
TRIP
ENA
41.
Figure
(nominal) = 1.8 V, and 1.5 V for
(nominal) = 2.5 V/3.3 V.
OUTPUT
INPUT
OR
(low) is 0.7 V. For V
is calculated as shown in the equation:
ENA
Measurements (Except Output Enable/Disable)
_
MEASURED
TRIP
40.
Figure 40. Voltage Reference Levels for AC
V
t
MEAS
DIS
(high) or V
DDEXT
t
ENA
is the interval, from when the reference sig-
DIS_MEASURED
=
t
=
(nominal) = 1.8 V—V
DIS_MEASURED
ENA
t
TRIP
ENA_MEASURED
is the interval from the point when a
TRIP
DDEXT
(low) is 1.0 V . Time t
and t
(low) trip voltage.
–
(nominal) = 2.5 V/3.3 V—
DECAY
t
DECAY
–
t
TRIP
as shown on the left
TRIP
MEAS
(high) is 1.3 V
TRIP
Rev. D | Page 45 of 60 | August 2006
is 0.95 V for
V
TRIP
MEAS
Figure 40
DIS
(high) or
is the
is the
The time for the voltage on the bus to decay by V is dependent
on the capacitive load C
can be approximated by the equation:
The time t
V
The time t
signal switches, to when the output voltage decays V from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the ADSP-BF531/ADSP-BF532
processor’s output voltage and the input threshold for the
device requiring the hold time. C
(per data line), and I
(per data line). The hold time will be t
put disable times as specified in the
Page 23
in
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
(nominal) = 1.8 V, and 1.5 V for V
2.5 V/3.3 V.
show how output rise time varies with capacitance. The delay
V equal to 0.1 V for V
DDEXT
(MEASURED)
(MEASURED)
SDRAM Interface Timing on Page
t
DIS
V
V
OUTPUT
OH
OL
Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
OUTPUT STOPS DRIVING
(nominal) = 2.5 V/3.3 V.
PIN
TO
(for example t
DECAY
DIS_MEASURED
Figure 43 on Page 46
DECAY
is calculated with test loads C
REFERENCE
t
V
V
Figure 41. Output Enable/Disable
DIS_MEASURED
OH
OL
SIGNAL
ADSP-BF531/ADSP-BF532
using the equation given above. Choose V
t
L
(MEASURED)
(MEASURED) + V
DECAY
t
is the total leakage or three-state current
Figure
DECAY
is the interval from when the reference
DSDAT
L
DDEXT
and the load current I
HIGH IMPEDANCE STATE
for an SDRAM write cycle as shown
30pF
=
42). V
(nominal) = 1.8 V or 0.5 V for
t
ENA
C
L
V
L
is the total bus capacitance
through
LOAD
DDEXT
Timing Specifications on
OUTPUT STARTS DRIVING
V
50
27).
DECAY
is 0.95 V for V
(nominal) =
I
L
t
ENA_MEASURED
Figure 54 on Page 48
V
V
plus the various out-
TRIP
TRIP
t
TRIP
L
I
(LOW)
and I
(HIGH)
. This decay time
V
V
OH
OL
(MEASURED)
(MEASURED)
V
L
LOAD
, and with
DDEXT