ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 38

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF531/ADSP-BF532
Serial Peripheral Interface (SPI) Port
—Slave Timing
Table 26
Table 26. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
SPICHS
SPICLS
SPICLK
HDS
SPITDS
SDSCI
SSPID
HSPID
DSOE
DSDHI
DDSPID
HDSPID
CPHA = 0
and
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
CPHA = 1
Figure 23
(INPUT)
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
(CPOL = 0)
(CPOL = 1)
SPISS
MOSI
MOSI
(INPUT)
(INPUT)
MISO
MISO
SCK
SCK
describe SPI port slave operations.
t
DSOE
t
DSOE
t
SDSCI
MSB VALID
t
t
t
DDSPID
t
SPICHS
SPICLS
MSB VALID
SSPID
t
Figure 23. Serial Peripheral Interface (SPI) Port—Slave Timing
DDSPID
MSB
Rev. D | Page 38 of 60 | August 2006
t
t
MSB
SPICLS
SPICHS
t
HDSPID
t
HSPID
t
SSPID
t
LSB VALID
DDSPID
t
t
SPICLK
SSPID
LSB
LSB VALID
V
Min
2t
2t
4t
2t
2t
2t
1.6
1.6
0
0
0
0
DDEXT
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
t
HSPID
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
= 1.8 V
t
t
DSDHI
HDS
t
LSB
DSDHI
Max
9
9
10
10
t
HSPID
t
SPITDS
V
Min
2t
2t
4t
2t
2t
2t
1.6
1.6
0
0
0
0
DDEXT
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
= 2.5 V/3.3 V
Max
8
8
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns