ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 42

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF531/ADSP-BF532
JTAG Test and Emulation Port Timing
Table 29
Table 29. JTAG Port Timing
1
2
3
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = DATA15–0, ARDY, TMR2–0, PF15–0, PPI_CLK, RSCLK0–1, RFS0–1, DR0PRI, DR0SEC, TSCLK0–1, TFS0–1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RX,
50 MHz maximum
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2–0, PF15–0, RSCLK0–1, RFS0–1,
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
RESET, NMI, BMODE1–0, BR, PP3–0.
TSCLK0–1, TFS0–1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, TX, BG, BGH, PPI3–0.
and
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK High
System Inputs Hold After TCK High
TRST Pulse Width
TDO Delay from TCK Low
System Outputs Delay After TCK Low
SYSTEM
OUTPUTS
TCK
TMS
TDO
TDI
INPUTS
SYSTEM
Figure 27
describe JTAG port operations.
2
(Measured in TCK Cycles)
t
DSYS
t
DTDO
t
1
SSYS
t
STAP
3
1
Rev. D | Page 42 of 60 | August 2006
t
TCK
Figure 27. JTAG Port Timing
t
HSYS
t
HTAP
V
Min
20
4
4
4
5
4
0
DDEXT
= 1.8 V V
Max
10
12
Min
20
4
4
4
5
4
0
DDEXT
= 2.5 V/3.3 V
Max
10
12
Unit
ns
ns
ns
ns
ns
ns
ns
TCK