ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 24

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF531/ADSP-BF532
Clock and Reset Timing
Table 15
Absolute Maximum Ratings on Page
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 400 MHz/133 MHz.
Table 15. Clock and Reset Timing
1
2
3
Parameter
Timing Requirements
t
t
t
t
If DF bit in PLL_CTL register is set, then the maximum t
Applies to bypass mode and nonbypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,
CKIN
CKINL
CKINH
WRST
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
and
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
CLKIN
Figure 10
RESET
describe clock and reset operations. Per
2
t
1
CKINL
t
CKIN
22, combinations of
t
CKINH
3
CKIN
period is 50 ns.
Rev. D | Page 24 of 60 | August 2006
Figure 10. Clock and Reset Timing
t
WRST
Min
25.0
10.0
10.0
11 t
CKIN
Max
100.0
1
Unit
ns
ns
ns
ns