XC2VP4 XILINX [Xilinx, Inc], XC2VP4 Datasheet - Page 108

• Manufacturer Part Number: XC2VP4
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs
• Manufacturer: XILINX [Xilinx, Inc]

Configuration Timing
Configuration Memory Clearing Parameters
Power-up timing of configuration signals is shown in
Table 46: Power-Up Timing Characteristics
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied
Power-on reset
Program latency
CCLK (output) delay
Program pulse width
directly to ground or V
R
Description
M0, M1, M2*
CCAUX
PROG_B
(Required)
or Input)
INIT_B
(Output
CCLK
V
. The mode pins should not be toggled during and after configuration.
CC
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Figure 7: Configuration Power-Up Timing
References
Figure
*Can be either 0 or 1, but must not toggle during and after configuration.
1
2
3
Figure
www.xilinx.com
1
T
POR
7; corresponding timing characteristics are listed in
2
T
PL
T
Symbol
PROGRAM
T
T
T
ICCK
POR
PL
T
ICCK
3
T
Value
PL
0.25
4.00
300
4
ds083-3_07_012004
+ 2
μ
s per frame, max
ms, max
μ
μ
ns, min
Units
s, max
s, min
Module 3 of 4
Table
46.
37