XC2VP4 XILINX [Xilinx, Inc], XC2VP4 Datasheet - Page 112

• Manufacturer Part Number: XC2VP4
• Description: Virtex-II Pro and Virtex-II Pro X Platform FPGAs
• Manufacturer: XILINX [Xilinx, Inc]

Virtex-II Pro Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
With DCM
Table 50: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
With DCM
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
2. Output timing is measured at 50% V
3. DCM output jitter is already included in the timing calculation.
LVCMOS25 Global Clock Input to Output
Delay using Output Flip-flop, 12 mA, Fast
Slew Rate, with DCM.
For data output with different standards,
adjust the delays with the values shown in
IOB Output Switching Characteristics
Standard Adjustments, page
Global Clock and OFF with DCM
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
R
Description
26.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
CC
threshold with test setup shown in
T
Symbol
ICKOFDCM
www.xilinx.com
XC2VPX20
XC2VPX70
XC2VP100
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
Figure
6. For other I/O standards, see
1.55
1.58
1.63
1.68
1.68
1.68
1.71
1.80
1.87
1.87
N/A
-7
Speed Grade
1.59
1.61
1.68
1.74
1.74
1.75
1.86
2.00
2.07
2.07
2.38
-6
1.62
1.65
1.72
1.79
1.79
1.80
1.92
2.07
2.24
2.24
2.45
-5
Table
Module 3 of 4
37.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41