MPC8358E_11 FREESCALE [Freescale Semiconductor, Inc], MPC8358E_11 Datasheet - Page 21

• Manufacturer Part Number: MPC8358E_11
• Description: PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Figure 5
6.2.2
Table 20
DDR and DDR2 SDRAM interface.
Freescale Semiconductor
At recommended operating conditions with GV
At recommended operating conditions with GV
MDQS—MDQ/MECC input skew per byte
Notes:
1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 ≤ n ≤ 7)
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
Skew between any MCK to ADDR/CMD
or ECC (MECC[{0...7}] if n = 8).
MDQS[n]
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
MDQ[x]
shows the input timing diagram for the DDR controller.
and
MCK[n]
MCK[n]
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 21
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source
Parameter
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications Mode
Parameter
provide the output AC timing specifications and measurement conditions for the
8
266 MHz
200 MHz
DD
DD
Figure 5. DDR Input Timing Diagram
of (1.8 or 2.5 V) ± 5%.
of (1.8 V or 2.5 V) ± 5%.
266 MHz
200 MHz
t
t
MCK
Symbol
DISKEW
t
DISKEW
Synchronous Mode
Symbol
t
AOSKEW
t
MCK
1
D0
–1125
–1250
Min
D1
–1.1
–1.2
Min
6
t
DISKEW
1125
1250
Max
Max
0.3
0.4
10
DDR and DDR2 SDRAM
Unit
ps
Unit
ns
ns
Notes
Notes
1, 2
2
3
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