MPC8358E_11 FREESCALE [Freescale Semiconductor, Inc], MPC8358E_11 Datasheet - Page 79

• Manufacturer Part Number: MPC8358E_11
• Description: PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

22.3
The QUICC Engine block PLL is controlled by the RCWL[CEPMF], RCWL[CEPDF], and
RCWL[CEVCOD] parameters.
block PLL.
Freescale Semiconductor
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
QUICC Engine Block PLL Configuration
Core VCO frequency = Core frequency × VCO divider. The VCO divider
(RCWL[COREPLL[0:1]]) must be set properly so that the core VCO
frequency is in the range of 800–1800 MHz. Having a core frequency below
the CSB frequency is not a possible option because the core frequency must
be equal to or greater than the CSB frequency.
RCWL[CEPMF] RCWL[CEPDF]
0–1
11
00
01
10
11
00
01
10
11
00
01
10
11
Table 72. QUICC Engine Block PLL Multiplication Factors
00000
00001
00010
00011
00100
RCWL[COREPLL]
Table 71. e300 Core PLL Configuration (continued)
Table 72
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
2–5
shows the multiplication factor encodings for the QUICC Engine
0
0
0
0
0
6
1
0
0
0
0
1
1
1
1
0
0
0
0
NOTE
Multiplication Factor = RCWL[CEPMF]/
core_clk : csb_clk
Ratio
1.5:1
2.5:1
2.5:1
2.5:1
2.5:1
2:1
2:1
2:1
2:1
3:1
3:1
3:1
3:1
(1 + RCWL[CEPDF])
QUICC Engine PLL
Reserved
× 16
× 2
× 3
× 4
VCO divider
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
8
2
4
8
8
2
4
8
8
2
4
8
8
Clocking
79