MPC8358E_11 FREESCALE [Freescale Semiconductor, Inc], MPC8358E_11 Datasheet - Page 76

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MPC8358E_11

Manufacturer Part Number
MPC8358E_11
Description
PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Clocking
22.1
The system PLL is controlled by the RCWL[SPMF] and RCWL[SVCOD] parameters.
multiplication factor encodings for the system PLL.
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in
76
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
System PLL Configuration
The VCO divider must be set properly so that the system VCO frequency is
in the range of 600–1400 MHz.
Table 68. System PLL Multiplication Factors
RCWL[SVCOD]
RCWL[SPMF]
Table 69. System PLL VCO Divider
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00
01
10
11
NOTE
Multiplication Factor
VCO Divider
System PLL
Reserved
Reserved
× 16
× 10
× 11
× 12
× 13
× 14
× 15
× 2
× 3
× 4
× 5
× 6
× 7
× 8
× 9
4
8
2
Freescale Semiconductor
Table
Table 68
69.
shows the

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