MC68HC05L28B MOTOROLA [Motorola, Inc], MC68HC05L28B Datasheet
MC68HC05L28B
Related parts for MC68HC05L28B
MC68HC05L28B Summary of contents
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HC05 MC68HC05L28 MC68HC705L28 TECHNICAL DATA MC68HC05L28/D !MOTOROLA ...
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MODES OF OPERATION AND PIN DESCRIPTIONS 16-BIT PROGRAMMABLE TIMER LIQUID CRYSTAL DISPLAY DRIVER MODULE CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS INTRODUCTION MEMORY AND REGISTERS INPUT/OUTPUT PORTS CORE TIMER I A/D CONVERTER RESETS AND INTERRUPTS MECHANICAL DATA ORDERING INFORMATION MC68HC705L28 ...
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INTRODUCTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS 3 MEMORY AND REGISTERS 4 INPUT/OUTPUT PORTS 5 CORE TIMER 6 16-BIT PROGRAMMABLE TIMER 7 LIQUID CRYSTAL DISPLAY DRIVER MODULE C-BUS 9 A/D CONVERTER 10 RESETS AND INTERRUPTS ...
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High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit All Trade Marks recognized. This document contains information on new products. Specifications and information herein are subject to change without notice. All products are sold on Motorola’s Terms & Conditions of Supply. ...
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Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low ...
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CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05L28/D) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, ...
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How could we improve this document? 9. How would you rate Motorola’s documentation? – In general – Against other semiconductor suppliers 10. Which semiconductor manufacturer provides the best technical documentation? 11. Which company (in any field) provides the best ...
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TABLE OF CONTENTS Paragraph Number 1.1 Features.................................................................................................................1-1 1.2 Mask options on the MC68HC05L28.....................................................................1-3 1.2.1 Option register (OPT).......................................................................................1-3 MODES OF OPERATION AND PIN DESCRIPTIONS 2.1 Modes of operation ................................................................................................2-1 2.1.1 MC68HC05L28 modes of operation ................................................................2-2 2.1.1.1 Single chip mode........................................................................................2-2 2.1.1.2 RAM ...
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Paragraph Number 3.1 Registers ...............................................................................................................3-1 3.2 LCD RAM ..............................................................................................................3-1 3.3 RAM ......................................................................................................................3-1 3.4 Programming registers ..........................................................................................3-3 3.4.1 EEPROM programming register (EEPROG) ...................................................3-3 3.4.1.1 CPEN — Charge pump enable ..................................................................3-3 3.4.1.2 ER1, ER0 — Erase select bits ...................................................................3-3 3.4.1.3 LATCH — ...
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Paragraph Number 16-BIT PROGRAMMABLE TIMER 6.1 Counter ..................................................................................................................6-3 6.1.1 Counter high register Counter low register Alternate counter high register Alternate counter low register ..........................................................................6-3 6.2 Timer functions ......................................................................................................6-4 6.2.1 Timer control registers .....................................................................................6-4 6.2.1.1 Timer control register 1 (TCR1)..................................................................6-4 6.2.1.2 ...
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Paragraph Number 8.3.7 Clock synchronization ......................................................................................8-5 8.3.8 Handshaking....................................................................................................8-5 8.4 Registers ...............................................................................................................8-6 2 8.4.1 I C-bus address register (MADR) ....................................................................8-6 2 8.4.2 I C-bus frequency divider register (FDR).........................................................8-6 2 8.4.3 I C-bus control register (MCR) ........................................................................8-7 2 8.4.4 I C-bus status ...
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Paragraph Number 10.2.2.3 Programmable 16-bit timer interrupt.........................................................10-7 2 10.2.2 interrupts ...........................................................................................10-8 10.2.3 Hardware controlled interrupt sequence ........................................................10-8 CPU CORE AND INSTRUCTION SET 11.1 Registers .............................................................................................................11-1 11.1.1 Accumulator (A) .............................................................................................11-1 11.1.2 Index register (X)............................................................................................11-2 11.1.3 Program counter (PC) ....................................................................................11-2 ...
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Paragraph Number 13.1 Pin configurations — 56-pin SDIP .......................................................................13-1 13.2 Mechanical dimensions — 56-pin plastic shrink dual-in-line (SDIP) ...................13-2 14.1 EPROM ...............................................................................................................14-1 14.2 Verification media ................................................................................................14-1 14.3 ROM verification units (RVU)...............................................................................14-2 A.1 Features ............................................................................................................... A-1 A.2 Modes of operation............................................................................................... A-1 ...
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LIST OF FIGURES Figure Number MC68HC05L28/ MC68HC705L28 block diagram....................................................1-2 1-1 2-1 RAM bootloader circuit ...........................................................................................2-3 MC68HC705L28 EPROM programming circuit ......................................................2-5 2-2 2-3 Oscillator connections ............................................................................................2-7 2-4 RC connection for external POR ............................................................................2-8 2-5 STOP flowchart ......................................................................................................2-11 2-6 WAIT flowchart .......................................................................................................2-13 ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA viii LIST OF FIGURES TPG MC68HC05L28 ...
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Table Number 2-1 MC68HC05L28 operating mode entry conditions ..................................................2-1 2-2 MC68HC705L28 operating mode entry conditions ................................................2-1 2-3 RAM bootloader mode jump vector (MC68HC05L28)............................................2-3 2-4 RAM bootloader mode jump vectors (MC68HC705L28) ........................................2-3 3-1 Erase mode select..................................................................................................3-3 3-2 Register outline.......................................................................................................3-6 4-1 I/O ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA x LIST OF TABLES TPG MC68HC05L28 ...
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INTRODUCTION The MC68HC05L28 is a flexible general-purpose microcomputer, particularly suited to applications throughout the consumer and automotive industries member of the highly successful Motorola M68HC05 family of microcomputers and includes many of the standard features of this ...
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LCD subsystem with 18 frontplanes and 4 backplanes • 16-bit programmable timer with 2 input capture and 2 output compare functions • 15-stage, multifunctional core timer, with overflow, real-time interrupt and computer operating properly (COP) watchdog timer (software ...
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Mask options on the MC68HC05L28 There is only one mask option on the MC68HC05L28. This is to enable or disable the STOP instruction programmed during manufacture and must be specified on the order form. 1.2.1 Option register ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 1-4 INTRODUCTION TPG MC68HC05L28 ...
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MODES OF OPERATION AND PIN DESCRIPTIONS 2.1 Modes of operation The MC68HC05L28 has two modes of operation available to the user – single chip and RAM bootloader. The MC68HC705L28 also has two modes of operation – single chip and EPROM/RAM ...
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MC68HC05L28 modes of operation 2 2.1.1.1 Single chip mode This is the normal operating mode of the MC68HC05L28 and the MC68HC705L28. In this mode the device functions as a self-contained microcomputer (MCU) with all on-board peripherals, including two 8-bit ...
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M 4.0 MHz 22pF 22pF V DD 100nF All resistors are 10 k unless specified otherwise Figure 2-1 RAM bootloader circuit Table 2-3 RAM bootloader mode jump vector (MC68HC05L28) Table 2-4 RAM bootloader mode jump vectors (MC68HC705L28) MC68HC05L28 MODES ...
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MC68HC705L28 modes of operation 2 2.1.2.1 EPROM bootloader mode This mode is used for programming the on-board EPROM. In bootloader mode the operation of the device is the same as in single chip mode, except that the vectors are ...
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L1 = VERIFY L2 = PROGRAM +5V + +5V PB7 +5V PB5 RESET VDD +5V TCAP1 TCAP2 VREFH PB2 PB3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 VREFL PA7 ADIN VPP IRQ0/VPP VSS MHz 22pF ...
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Pin descriptions 2 Pin assignments are shown in Section 13. 2.2.1 VDD and VSS Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS is ground the nature of ...
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OSC1, OSC2 These pins provide control input for an on-chip oscillator circuit. A crystal connected to these pins supplies the oscillator clock. The oscillator frequency (f bus frequency ( MCU OSC1 OSC2 OSC1 ...
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Crystal 2 The circuit shown in Figure 2-3(a) is recommended when using a crystal . Figure 2-3(d) lists the recommended capacitance and feedback resistance values. The internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal resonator ...
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PA0 – PA7, PB0 – PB7 These 16 I/O lines comprise ports A and B. The state of any pin is software programmable, and all the pins are configured as inputs during power-on or reset. Port B pins in ...
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Low power modes 2 2.3.1 STOP The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the internal oscillator is turned off, halting all internal processing, including timer (and COP watchdog timer) operation. During ...
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MC68HC05L28 MODES OF OPERATION AND PIN DESCRIPTIONS STOP Stop oscillator and all clocks Clear I-bit No Reset Yes External No interrupt (IRQ0,1,2) Yes Turn on oscillator Wait for time delay to stabilize 1. Fetch reset vector or 2. Service interrupt: ...
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WAIT 2 The WAIT instruction places the MCU in a low power consumption mode, but the WAIT mode consumes more power than the STOP mode. All CPU action is suspended, but the core timer, 2 16-bit timer and I ...
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WAIT Oscillator active Timer clock active Processor clocks stopped Reset Yes 1. Fetch reset vector or 2. Service interrupt: a. stack b. set I-bit c. vector to interrupt routine MC68HC05L28 MODES OF OPERATION AND PIN DESCRIPTIONS External No No interrupt ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA MODES OF OPERATION AND PIN DESCRIPTIONS 2-14 TPG MC68HC05L28 ...
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MEMORY AND REGISTERS The MC68HC05L28 has a 16K byte memory map consisting of registers, user ROM, user RAM, bootstrap ROM, LCD RAM, EEPROM and I/O, as shown in Figure 3-1. 3.1 Registers All the I/O, control and status registers of ...
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LCD RAM (12 bytes) $004C Reserved $0080 $00C0 (256 bytes) Stack $00FF $0180 Reserved $0300 EEPROM (240 bytes) $03F0 Reserved $1000 User ROM (8176 bytes) User EPROM (8128bytes) $2FC0/$2FF0 Reserved $3F00 Bootstrap ROM (240 bytes) ...
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Programming registers 3.4.1 EEPROM programming register (EEPROG) Address EEPROM program (EEPROG) $001B 3.4.1.1 CPEN — Charge pump enable This bit enables the charge pump which produces the internal programming voltage set with the LATCH bit and should ...
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LATCH — EEPROM latch control 1 (set) – The EEPROM address and data buses are configured for programming. This causes the address and data buses to be latched when a write to EEPROM is carried out. EEPROM cannot be ...
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ELAT — EPROM latch control 1 (set) – When this bit is set to 1, the EPROM address and data buses are configured for programming. This causes the address and data buses to be latched when a write to ...
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Register Name Port A data (PORTA) 3 Port B data (PORTB) Reserved Reserved Port A data direction (DDRA) Port B data direction (DDRB) Reserved Reserved Core timer control/status (CTCSR) Core timer counter (CTCR) IRQ1 IRQ2 Reserved Reserved Reserved Reserved 2 ...
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Register Name Address bit 7 Timer counter high (TCH) $0028 Timer counter low (TCL) $0029 Alternate counter high (ACH) $002A Alternate counter low (ACL) $002B Timer control 1 (TCR1) $002C Timer control 2 (TCR2) $002D Timer status (TSR) $002E Reserved ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 3-8 MEMORY AND REGISTERS TPG MC68HC05L28 ...
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INPUT/OUTPUT PORTS In single chip mode, the MC68HC05L28 has a total of 22 I/O lines, arranged as two 8-bit ports (A and B) and one 6-bit port (D). Each I/O line is individually programmable as either input or output, under ...
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Data direction register bit Latched data register bit 4 4.2 Ports A and B These ports are standard M68HC05 bidirectional I/O ports, each comprising a data register and a data direction register. Reset does not affect the state of the ...
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Port data registers (PORTA, PORTB and PORTD) Address Port A data (PORTA) $0000 Port B data (PORTB) $0001 Port D data (PORTD) $0030 Each bit can be configured as input or output via the corresponding data direction bit in ...
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Port D select register (SELD) Port D select (SELD) Setting bits 5-0 in the port D select register to logical ‘1’ configures the pin to be dedicated to the 2 timer or the I C bus subsystems. This ...
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PD2/TCAP2 — Port D pin 2/TCAP2 select 1 (set) – This pin is configured as timer input capture 2 input. Clearing bit 2 in the COND register enables the pull-up resistor. 0 (clear) – This pin is configured as I/O ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 4-6 INPUT/OUTPUT PORTS TPG MC68HC05L28 ...
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The MC68HC05L28 has a 15-stage ripple counter called the core timer (CTIMER). Features of this timer are: timer overflow, power-on reset (POR), real time interrupt (RTI) with four selectable interrupt rates, and a computer operating properly (COP) watchdog timer. (Core ...
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As shown in Figure 5-1, the timer is driven by the internal bus clock divided by four with a fixed prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the ...
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Computer operating properly (COP) watchdog timer The COP watchdog timer is implemented by dividing the output of the RTI circuit by eight, as shown in Figure 5-1. The minimum COP timeout period is seven times the RTI period. This ...
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RTIF — Real time interrupt flag 1 (set) – A real time interrupt has occurred. 0 (clear) – No real time interrupt has been generated. This bit is set when the output of the chosen stage becomes active; an interrupt ...
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Core timer counter register (CTCR) Address Core timer counter (CTCR) $0009 The core timer counter register is a read-only register, which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. Reset clears ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 5-6 CORE TIMER TPG MC68HC05L28 ...
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PROGRAMMABLE TIMER The MC68HC05L28 has a 16-bit programmable timer. This timer consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler, plus input capture/output compare circuitry. Selected input edges cause the current counter value to be latched ...
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High Low High byte byte Output $22 compare compare $23 register 1 register 2 6 Output compare compare circuit 1 circuit 2 IC1F IC2F OC1F TOF Figure 6-1 16-bit programmable timer block diagram MOTOROLA 6-2 Internal bus Internal 8-bit processor ...
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Counter The key element in the programmable timer is a 16-bit, free-running counter, or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution ...
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Bits 8–15 — MSB of counter/alternate counter register A read of only the more significant byte (MSB) transfers the LSB to a buffer, which remains fixed after the first MSB read, until the LSB is also read. Bits 0–7 — ...
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TOIE — Timer overflow interrupt enable 1 (set) – Timer overflow interrupt enabled. 0 (clear) – Timer overflow interrupt disabled. CO1E — Timer compare 1 output enable 1 (set) – Output of timer compare 1 is enabled. 0 (clear) – ...
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Timer control register 2 (TCR2) Timer control 2 (TCR2) OC2IE — Output compare 2 interrupt enable 1 (set) – Output compare 2 interrupt enabled. 0 (clear) – Output compare 2 interrupt disabled. CO2E — Timer compare 2 output enable ...
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Timer status register (TSR) The timer status register ($2E) contains the status bits for the interrupt conditions — ICF, OCF, TOF. Accessing the timer status register satisfies the first condition required to clear the status bits. The remaining step ...
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When using the timer overflow function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally cleared if: – the timer status register is read or ...
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Input capture registers ‘Input capture’ technique whereby an external signal (connected to the TCAP1 or TCAP2 pin) is used to trigger a read of the free-running counter. In this way it is possible to relate the timing ...
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Input capture register 2 Input capture high 2 (ICH2) Input capture low 2 (ICL2) The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used to latch the value of the free-running ...
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Output compare registers ‘Output compare’ technique that may be used, for example, to generate an output waveform signal when a specific time period has elapsed, by presetting the output compare register to the appropriate value. ...
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Output compare register 2 Output compare high 2 (OCH2) Output compare low 2 (OCL2) The 16-bit output compare register 2 is made up of two 8-bit registers at locations $26 (MSB) and $27 (LSB). The contents of the output ...
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Timer during WAIT mode In WAIT mode all CPU action is suspended, whereas the timer continues to run. 6.4 Timer during STOP mode In the STOP mode all MCU clocks are stopped, so the timer stops counting. If STOP ...
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Internal processor clock Internal reset Internal timer clocks 16-bit counter External reset or end of POR Note: 6 Internal processor clock Internal timer clocks 16-bit counter Input edge Internal capture latch Input capture register Input capture flag Note: If the ...
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Internal processor clock T00 T01 Internal timer clocks T10 T11 16-bit counter Output compare CPU writes $F457 register Compare register latch Output compare flag and TCMP Note: (1) The CPU write to the compare registers may take place at any ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 6-16 16-BIT PROGRAMMABLE TIMER TPG MC68HC05L28 ...
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LIQUID CRYSTAL DISPLAY DRIVER MODULE This chapter describes the generic M68HC05 family LCD driver module. Any differences in the module specific to the MC68HC05L28 are indicated along with the generic description. The M68HC05 family LCD driver module can be configured ...
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LCD RAM Data to be displayed on the LCD must be written into the LCD RAM. The LCD RAM is comprised of 12 bytes of RAM (in the MC68HC05L28’s memory map) at $0040 – $004B. The 96 bits in ...
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The operating mode is selected at power on using the multiplex ratio bits (MUX3 and MUX4) in the LCD control register as shown in Table 7- recommended that the DISON bit in the LCD register is not set ...
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Hz instead can be obtained. See Section 7.4. Figure 7-3 to Figure 7-6 show the backplane waveforms and some examples of frontplane waveforms for each of ...
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LCD V2 BP0 LCD V2 BP1 FPx, example LCD V2 FPx, example LCD V2 FPx, example 3 V1 ...
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BP0 BP1 BP2 FPx, example FPx, example FPx, example 3 MOTOROLA 7-6 LCD LCD V2 V1 ...
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LCD V2 BP0 LCD V2 BP1 LCD V2 BP2 LCD V2 BP3 LCD V2 FPx, example 1 ...
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LCD control register LCD control register (LCD) VLCDON — LCD voltage select The V option is not available on the MC68HC05L28 or MC68HC705L28, therefore, this bit must LCD be cleared. FDISP — Display frequency 1 (set) – An extra ...
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I C-bus is a two-wire, bidirectional serial bus that provides a simple, efficient way to exchange data between devices. Being a two-wire device, the I connections between devices, and eliminates the need for an address decoder. The bus is ...
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I C-bus system configuration 2 The I C-bus system uses a serial data line and a serial clock line for data transfer. All the devices connected to it must have open drain or open collector outputs. A logic ...
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Figure 8-1 I MC68HC05L28 2 C bus transmission signal diagrams 2 I C-BUS 8 TPG MOTOROLA 8-3 ...
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Data transfer Once successful slave addressing has been achieved, the data transfer can proceed byte by byte, in the direction specified by the R/W bit. Data can be changed only when SCL is low and must be held stable ...
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Clock synchronization Since wired-AND logic is performed on the SCL line, a high to low transition on SCL affects all the devices connected on the bus. The devices start counting their low period and once a device’s clock has ...
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Registers 2 8.4.1 I C-bus address register (MADR C-bus address register (MADR) ADR7 – ADR1 — Slave address bits These bits define the slave address of the I the MAAS bit in the MSR register (see Section ...
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MCB4-0 Divider MCB4-0 Divider ...
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MSTA — Master/slave mode select 1 (set) – Master mode; send START signal when set. 0 (clear) – Slave mode; send STOP signal when cleared. This bit is cleared on reset. When MSTA is changed from ...
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MBB — Bus busy 1 (set) – Bus is busy. 0 (clear) – Bus is idle. This bit indicates the status of the bus. When a START signal is detected, MBB is set. When a STOP signal is detected, MBB ...
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I C-bus data register (MDR C-bus data register (MDR) These bits can be read and written at any time. In master transmit mode, a write to this register will cause the data ...
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TXSTART BSET BSET LDA STA CLI 8.5.3 Software response The transmission or reception of a byte sets the data transferring bit, MCF, which indicates that one byte of communication is finished. Also, the C-bus interrupt (if MIEN ...
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Generation of a STOP signal A data transfer ends with a STOP signal generated by the master device. A master transmitter can simply generate a STOP signal after all the data has been transmitted; for example: MASTX BRSET LDAA ...
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RESTART BCLR BSET LDAA STAA 8.5.6 Slave mode In the slave interrupt service routine, the MAAS bit should be tested to check if a calling of its own address has just been received. If MAAS is set, software should set ...
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Last byte transmitted RXAK = 0? Yes Write next byte to MDR Figure 8-3 Example of a typical I MOTOROLA 8-14 Clear MIF No Master mode? Yes TX RX TX/ RX? Yes No Yes Set TXAK = 1 ...
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Clear MAL No MAAS = 1? Yes Yes SRW = 1? No Set TX mode Set RX mode Dummy read from Write to MDR Figure 8-3 Example of a typical I MC68HC05L28 Yes Arbitration lost? Yes MAAS = 1? Yes ...
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THIS PAGE LEFT BLANK INTENTIONALLY 8 MOTOROLA 8- C-BUS TPG MC68HC05L28 ...
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A/D CONVERTER The analog to digital converter system consists of a single 8-bit successive approximation converter and a 16-channel multiplexer. There are only two A/D channels available on the MC68HC05L28. These are connected to the ADx pins of the MC68HC05L28 ...
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AD0 AD1 VRH (VRH+VRL)/2 VRL The result of each successive comparison is stored in the SAR and, when the conversion is 9 complete, the contents of the SAR are transferred to the read-only result data register ($17), and the conversion ...
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A/D registers 9.2.1 A/D status/control register (ADSTAT) Address A/D status/control register (ADSTAT) $0015 COCO ADRC ADON 9.2.1.1 COCO — Conversion complete flag 1 (set) – COCO flag is set each time a conversion is complete, allowing the new result ...
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Power-on or external reset will clear the ADON bit, disabling the A/D converter. ADRC 9.2.1.4 CH3 – CH0 — A/D channels and 0 The CH3–CH0 bits allow the user to determine which channel ...
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A/D input register (ADIN) Address A/D input register (ADIN) $0016 The ADIN register allows the A/D input to be read as a static input. Reading this register during an A/D conversion sequence may inject noise into the analog input ...
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ADx analog input The external analog voltage value to be processed by the A/D converter is sampled on an internal capacitor through a resistive path, provided by input-selection switches and a sampling aperture time switch, as shown in Figure ...
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RESETS AND INTERRUPTS 10.1 Resets The MC68HC05L28 can be reset in three ways: by the initial power-on reset function active low input to the RESET pin and by a COP watchdog timer reset, if the watchdog timer is ...
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Computer operating properly (COP) reset The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. Note: COP timeout is prevented by periodically writing a ‘0’ to ...
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Source Reset Software interrupt (SWI) External interrupt (IRQ) Core timer Programmable timer 10.2.1 Non-maskable software interrupt (SWI) The software interrupt (SWI executable instruction and a non-maskable interrupt executed regardless of the state of ...
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Yes External interrupt? 10 MOTOROLA 10-4 From RESET Is I-bit set? No Yes IRQ0,1,2 Clear IRQ0,1,2 No Yes Core timer interrupt Yes I C interrupt? No Yes TIMER16 interrupt? No Fetch next instruction SWI Yes instruction ? No ...
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External interrupt (IRQ0, IRQ1, IRQ2) These external interrupt sources use the same interrupt vector ($3FFA, $3FFB) IRQ0 If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I-bit ...
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IRQ1RST — IRQ1 reset The IRQ1 interrupt is cleared by writing a ‘1’ to this bit. This bit is write-only and always returns zero. IRQ1VAL — IRQ1 pin status The IRQ1VAL bit reflects current status of the IRQ1 pin. IRQ2 ...
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Table 10-3 IRQ2 interrupt sensitivity IRQ2LV IRQ2RST — IRQ2 reset The IRQ2 interrupt is cleared by writing a ‘1’ to this bit. This bit is write-only and always returns zero. IRQ2VAL — IRQ2 pin status The ...
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I C interrupts There is an interrupt flag and three status flags for the I and enabled. These interrupts will vector to the service routine located at the address specified by the contents of memory locations $3FF6 and ...
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CPU CORE AND INSTRUCTION SET This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05L28. 11.1 Registers The MCU contains five registers, as shown in the programming model of Figure ...
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Increasing memory address Unstack 11.1.2 Index register (X) The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area. ...
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Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, all maskable interrupts are masked interrupt occurs while ...
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Register/memory Instructions Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump ...
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Operation Description Condition codes Source Form Table 11-2 Register/memory instructions Immediate Function Load A from memory LDA A6 Load X from memory LDX AE Store A in memory STA Store X in memory STX Add memory to A ADD AB ...
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Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear ...
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Table 11-5 Read/modify/write instructions Function Increment INC Decrement DEC Clear CLR Complement COM 43 Negate (two’s complement) NEG Rotate left through carry ROL Rotate right through carry ROR Logical shift left LSL Logical shift right LSR Arithmetic shift right ASR ...
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Mnemonic INH ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET 11 BSR CLC CLI CLR CMP Address mode abbreviations BSC ...
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Table 11-7 Instruction set (Continued) Mnemonic INH IMM DIR COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA ...
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MOTOROLA 11-10 Table 11-8 M68HC05 opcode map CPU CORE AND INSTRUCTION SET TPG MC68HC05L28 ...
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Addressing modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the ...
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Extended In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte ...
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Relative The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are ...
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THIS PAGE LEFT BLANK INTENTIONALLY 11 MOTOROLA 11-14 CPU CORE AND INSTRUCTION SET TPG MC68HC05L28 ...
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ELECTRICAL SPECIFICATIONS This section contains the electrical specifications and associated timing information for the MC68HC05L28. 12.1 Maximum ratings Rating (1) Supply voltage Input voltage: Normal operations Bootloader mode (IRQ0 pin only) Current sink into port B Operating temperature range MC68HC05L28 ...
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Thermal characteristics and power considerations The average chip junction temperature, T equation: where Ambient Temperature ( Package Thermal Resistance, Junction-to-ambient ( C/ Internal Chip Power = I ...
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DC electrical characteristics for 5V operation Table 12-3 DC electrical characteristics (V = 5.0 Vdc 10 Vdc Characteristic Output voltage I = – LOAD I = +10 A LOAD Output high ...
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AC electrical characteristics for 5V operation Frequency of operation crystal external clock Internal operating frequency crystal external clock Cycle time Crystal oscillator start-up time Stop recovery start-up time (crystal oscillator) RESET pulse width Interrupt pulse width low (edge-triggered) (1) ...
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A/D converter characteristics Table 12-5 A/D converter characteristics Characteristics Resolution (1) Absolute Accuracy (2) Conversion Range V REFH V REFL Power up time Input leakage AD5 – AD0 Pin under test = VSS – 0.3V Pin under test = ...
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THIS PAGE LEFT BLANK INTENTIONALLY 12 MOTOROLA 12-6 ELECTRICAL SPECIFICATIONS TPG MC68HC05L28 ...
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MECHANICAL DATA 13.1 Pin configurations — 56-pin SDIP VPP /IRQ0 RESET Figure 13-1 56-pin SDIP pinout for the MC68HC05L28/ MC68HC705L28 MC68HC05L28 13 VSS 1 56 PB7 VDD 2 55 PB6 IRQ2 3 54 PB5 IRQ1 4 53 PB4 52 5 ...
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Mechanical dimensions — 56-pin plastic shrink dual-in-line (SDIP Base Plane B Dim. Min. Max. A – 5.08 A 0.51 – 0.38 0.56 B 0.76 1. 0.20 0.30 D 57.40 ...
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... If desired, Motorola will program blank EPROMs (supplied by the customer) from the data file used to create the custom mask, to aid in the verification process. MC68HC05L28 14 Package type Temperature 56-pin SDIP +70 C ORDERING INFORMATION Part number MC68HC05L28B MC68HC705L28B 14 TPG MOTOROLA 14-1 ...
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ROM verification units (RVU) Ten MCUs containing the customer’s ROM pattern will be provided for program verification. These units will have been made using the custom mask but are for ROM verification only. For expediency, they are usually unmarked ...
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MC68HC705L28 This appendix summarises the differences between the MC68HC05L28 and the MC68HC705L28. The same information can also be found in appropriate sections of the book. The MC68HC705L28 is an EPROM version of the MC68HC05L28. The 8176 bytes of user ROM ...
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A.2.1 Single chip mode This is the normal operating mode of the MC68HC705L28. In this mode the device functions as a self-contained microcomputer (MCU) with all on-board peripherals, including two 8-bit I/O ports and one 6-bit I/O port, available to ...
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Note: The EPROM must be erased before performing a program cycle VERIFY L2 = PROGRAM +5V + +5V PB7 +5V PB5 RESET VDD +5V TCAP1 TCAP2 VREFH PB2 PB3 PA0 PA1 PA2 PA3 PA4 PA5 PA6 ...
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A.2.3 RAM bootloader mode In addition to the EPROM bootloader mode on the MC68HC705L28, there is a RAM bootloader mode that allows the user to perform simple load and execute instructions in ROM. To make use of this feature a ...
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A.4 EPROM programming register (PCR) Address EPROM program (PCR) $001C A.4.1 ELAT — EPROM latch control 1 (set) – When this bit is set to 1, the EPROM address and data buses are configured for programming. This causes the address ...
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A.5 Pin configurations — 56-pin SDIP Figure A-2 56-pin SDIP pinout for the MC68HC705L28 A.6 Ordering information A 16K byte EPROM programmed with the customer’s software (positive logic for address and data) should be submitted for pattern generation. All unused ...
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This section contains abbreviations and specialist words used in this data sheet and throughout the industry. Further information on many of the terms may be gleaned from Motorola’s M68HC11 Reference Manual, M68HC11RM/ from a variety of standard electronics ...
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EVS Evaluation system. One of the range of platforms provided by Motorola for evaluation and emulation of their devices. HCMOS High-density complementary metal oxide semiconductor. A semiconductor technology chosen for its low power consumption and good noise immunity. I/O Input/output; ...
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Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are permanently connected to either ground or V PWM Pulse width modulation. This term is used to describe a technique where the width of the high and ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA iv GLOSSARY TPG MC68HC05L28 ...
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In this index numeric entries are placed first; page references in italics indicate that the reference figure. 56-pin SDIP mechanical dimensions 13-2 , 56-pin SDIP package 13-1 A – accumulator 11-1 A/D converter block diagram ...
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CTOF bit in CTCSR 5-3 CTOFE bit in CTCSR 5-4 D data retention mode 2-12 data transfer 8-4 DDRA, DDRB, DDRD — port data direction registers 4-3 direct addressing mode 11-11 DISON bit in LCD 7-8 E EEPGM bit in ...
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L LATCH bit in EEPROG 3-4 LCD block diagram 7-1 during WAIT mode 7-8 pins 2-9 , RAM 3-1 7-2 – timing diagrams 7-3 7-7 timing signals 7-3 voltage level selection 7-3 LCD — LCD control register DISON – LCD ...
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I/O programming 4-1 pin states 4-1 port D 4-2 port D configuration 4-4 port D control register 4-4 port D select register 4-4 port data registers 4-3 port structure 4-2 ports A and B 4-2 ...
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X X – index register 11-2 Z Z-bit in CCR 11-3 MC68HC05L28 INDEX TPG MOTOROLA ix ...
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THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA x INDEX TPG MC68HC05L28 ...
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CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05L28/D) Motorola wishes to continue to improve the quality of its documentation. We would welcome your feedback on the publication you have just received. Having used the document, please complete this card (or a photocopy of it, ...
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How could we improve this document? 9. How would you rate Motorola’s documentation? – In general – Against other semiconductor suppliers 10. Which semiconductor manufacturer provides the best technical documentation? 11. Which company (in any field) provides the best ...
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MODES OF OPERATION AND PIN DESCRIPTIONS 16-BIT PROGRAMMABLE TIMER LIQUID CRYSTAL DISPLAY DRIVER MODULE CPU CORE AND INSTRUCTION SET ELECTRICAL SPECIFICATIONS INTRODUCTION MEMORY AND REGISTERS INPUT/OUTPUT PORTS CORE TIMER I A/D CONVERTER RESETS AND INTERRUPTS MECHANICAL DATA ORDERING INFORMATION MC68HC705L28 ...
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INTRODUCTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS 3 MEMORY AND REGISTERS 4 INPUT/OUTPUT PORTS 5 CORE TIMER 6 16-BIT PROGRAMMABLE TIMER 7 LIQUID CRYSTAL DISPLAY DRIVER MODULE C-BUS 9 A/D CONVERTER 10 RESETS AND INTERRUPTS ...
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Literature Distribution Centres: EUROPE: Motorola Ltd., European Literature Centre, 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. ASIA PACIFIC: Motorola Semiconductors (H.K.) Ltd., Silicon Harbour Center, No. 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong ...