MC68HC05L28B MOTOROLA [Motorola, Inc], MC68HC05L28B Datasheet - Page 71

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MC68HC05L28B

Manufacturer Part Number
MC68HC05L28B
Description
Flexible general-purpose microcomputer
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
MC68HC05L28
Note:
Compare register
Note:
timer clocks
timer clocks
Output compare
Output compare
processor clock
processor clock
flag and TCMP
Timer overflow
(1) The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state
T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.
(2) The output compare flag is set at the timer state T11 that follows the comparison match ($F457 in this
example).
Internal
Internal
Internal
counter
register
Internal
counter
Figure 6-4 Timer state timing diagram for output compare
16-bit
16-bit
latch
Figure 6-5 Timer state timing diagram for timer overflow
flag
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleare
by a read of the timer status register during the internal processor clock high time, followed by a rea
of the counter low register.
T00
T01
T10
T11
T00
T01
T10
T11
16-BIT PROGRAMMABLE TIMER
CPU writes $F457
$FFFF
$F456
(Note 1)
(Note 1)
(Note 2)
$F457
$0000
$F458
$0001
$F457
$F459
$0002
MOTOROLA
TPG
6-15
6

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