MC68HC05L28B MOTOROLA [Motorola, Inc], MC68HC05L28B Datasheet - Page 93
MC68HC05L28B
Manufacturer Part Number
MC68HC05L28B
Description
Flexible general-purpose microcomputer
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC05L28B.pdf
(156 pages)
- Current page: 93 of 156
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RESTART
8.5.6
In the slave interrupt service routine, the MAAS bit should be tested to check if a calling of its own
address has just been received. If MAAS is set, software should set the transmit/receive mode
select bit (MTX) according to the R/W command bit, SRW. Writing to the MCR clears the MAAS
bit automatically. A data transfer may then be initiated by writing to MDR or by performing a dummy
read from MDR.
In the slave transmitter routine, the received acknowledge bit (RXAK) must be tested before
transmitting the next byte of data. If RXAK is set, this means an ‘end of data’ signal from the master
receiver, which must then switch from transmitter mode to receiver mode by software. This is followed
by a dummy read, which releases the SCL line so that the master can generate a STOP signal.
8.5.7
Only one master can engage the device at one time. Those devices wishing to engage the bus, but
having lost arbitration, are immediately switched to slave receive mode by hardware. Their data output
to the SDA line is stopped, but the internal transmitting clock is still generated until the end of the byte
during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this transfer
with MAL = 1 and MSTA = 0. If one master attempts to start transmission while the bus is being
engaged by another master, the hardware inhibits the transmission; the MSTA bit is cleared without
generating a STOP condition, an interrupt is generated, and MAL is set to indicate that the attempt to
engage the bus has failed. In these cases, the slave interrupt service routine should test MAL first; if
MAL is set, it should be cleared by software.
8.5.8
During STOP mode, the I
During WAIT mode, the I
slave mode. If the interrupt is enabled, the CPU comes out of WAIT mode after the end of a byte
of transmission.
MC68HC05L28
Slave mode
Arbitration lost
Operation during STOP and WAIT modes
BCLR
BSET
LDAA
STAA
2
2
C-bus is idle, but ‘wakes up’ when it receives a valid start condition in
C-bus is disabled.
5,MCR
5,MCR
CALLING
MDR
I
2
C-BUS
;ANOTHER START (RESTART) IS
;GENERATED BY
;THESE TWO CONSECUTIVE
;INSTRUCTIONS
;GET THE CALLING ADDRESS
;TRANSMIT THE CALLING ADDRESS
MOTOROLA
TPG
8-13
8
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