MC68HC05L28B MOTOROLA [Motorola, Inc], MC68HC05L28B Datasheet - Page 115
MC68HC05L28B
Manufacturer Part Number
MC68HC05L28B
Description
Flexible general-purpose microcomputer
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC05L28B.pdf
(156 pages)
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MC68HC05L28
Load A from memory
Load X from memory
Store A in memory
Store X in memory
Add memory to A
Add memory and carry to A
Subtract memory
Subtract memory from A
with borrow
AND memory with A
OR memory with A
Exclusive OR memory with A
Arithmetic compare A
with memory
Arithmetic compare X
with memory
Bit test memory with A
(logical compare)
Jump unconditional
Jump to subroutine
Function
Description
Operation
Condition
Source
codes
Form
AND
ORA
ADD
EOR
LDA
LDX
ADC
SUB
CMP
STX
JMP
STA
SBC
CPX
JSR
BIT
Table 11-2 Register/memory instructions
CPU CORE AND INSTRUCTION SET
AE
AB
A4
AA
A6
A0
A8
A9
A2
A1
A3
A5
Immediate
Multiplies the eight bits in the index register by the eight
bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
Table 11-1 MUL instruction
2
2
2
2
2
2
2
2
2
2
2
Addressing mode
2
2
2
2
2
2
2
2
2
2
2
2
Inherent
2
BE
BB
BA
B6
B4
B8
B9
B0
B1
B2
B3
B5
BC
BD
B7
BF
Direct
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
H : Cleared
N : Not affected
Z : Not affected
C : Cleared
I : Not affected
3
3
3
3
3
3
X:A
3
3
3
3
3
3
4
4
2
5
Cycles
CE
CB
CA
MUL
C6
C4
C8
C9
C0
C1
C2
C3
C5
CC
CD
C7
CF
11
Extended
X*A
3
3
3
3
Addressing modes
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
Bytes
4
5
5
3
6
1
FE
FB
FA
F6
F4
F8
F9
F0
F1
F2
F3
FC
FD
F5
F7
FF
Indexed
offset)
1
1
1
1
1
1
1
1
1
1
1
Opcode
(no
1
1
1
1
1
$42
3
3
3
3
3
3
3
3
3
3
3
3
4
2
5
4
EA
EE
EB
E4
E8
E6
E9
E0
E1
E2
E3
EC
ED
E5
EF
E7
Indexed
offset)
2
2
2
(8-bit
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
3
6
5
5
MOTOROLA
DE
DA
DB
D4
D8
D6
D9
D0
D1
D2
D3
DC
DD
D5
DF
D7
Indexed
(16-bit
offset)
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
TPG
5
5
5
11-5
5
5
5
5
5
5
5
5
5
4
7
6
6
11
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