MC68HC05L28B MOTOROLA [Motorola, Inc], MC68HC05L28B Datasheet - Page 119

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MC68HC05L28B

Manufacturer Part Number
MC68HC05L28B
Description
Flexible general-purpose microcomputer
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
MC68HC05L28
Mnemonic
BSC Bit set/clear
BTB Bit test & branch
DIR
EXT Extended
INH
STOP
COM
WAIT
EOR
NEG
NOP
ORA
ROR
CPX
DEC
JMP
MUL
ROL
RSP
SBC
SEC
SUB
JSR
LDA
LDX
LSR
RTS
STX
SWI
TST
TXA
LSL
STA
TAX
INC
SEI
RTI
Direct
Inherent
Address mode abbreviations
INH
IMM
Not implemented
IX2
IMM
IX
IX1
REL
Table 11-7 Instruction set (Continued)
DIR
CPU CORE AND INSTRUCTION SET
Indexed, 2 byte offset
Relative
Immediate
Indexed (no offset)
Indexed, 1 byte offset
EXT REL
Addressing modes
IX
IX1
H
N
Z
C
I
Half carry (from bit 3)
Negate (sign bit)
Zero
Carry/borrow
Interrupt mask
IX2
BSC BTB
Condition code symbols
1
H
0
?
0
?
Condition codes
Cleared
Set
Tested and set if true,
cleared otherwise
Not affected
Load CCR from stack
I
0
?
1
0
1
N
?
0
Z
MOTOROLA
?
C
?
1
0
1
TPG
11-9
11

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