MC68HC05L28B MOTOROLA [Motorola, Inc], MC68HC05L28B Datasheet - Page 62

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MC68HC05L28B

Manufacturer Part Number
MC68HC05L28B
Description
Flexible general-purpose microcomputer
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
6
6.2.1.2 Timer control register 2 (TCR2)
OC2IE — Output compare 2 interrupt enable
CO2E — Timer compare 2 output enable
Reset clears this bit.
OLVL2 — Output level 2
This bit determines the level that is clocked into the output level register by the next successful
output compare 2 and which will appear on the TCMP2 pin.
When OLVL2 is set, a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
that will appear on the TCMP2 pin.
Bits 1, 2 4, 6 and 7 — unused; always read 0.
MOTOROLA
6-6
Timer control 2 (TCR2)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Output compare 2 interrupt enabled.
Output compare 2 interrupt disabled.
Output of timer compare 2 is enabled.
Output of timer compare 2 is disabled.
A high output level will appear on the TCMP2 pin.
A low output level will appear on the TCMP2 pin.
Address
$002D
16-BIT PROGRAMMABLE TIMER
bit 7
0
bit 6
0
OC2IE
bit 5
bit 4
0
CO2E
bit 3
0
bit 2
0
bit 1
OLVL2 0000 0000
MC68HC05L28
bit 0
on reset
State
TPG

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