MC68HC05L28B MOTOROLA [Motorola, Inc], MC68HC05L28B Datasheet - Page 34
MC68HC05L28B
Manufacturer Part Number
MC68HC05L28B
Description
Flexible general-purpose microcomputer
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC05L28B.pdf
(156 pages)
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2
2.3.2
The WAIT instruction places the MCU in a low power consumption mode, but the WAIT mode
consumes more power than the STOP mode. All CPU action is suspended, but the core timer,
16-bit timer and I
will cause the MCU to exit WAIT mode.
During WAIT mode, the I-bit in the CCR is cleared to enable interrupts. All other registers, memory
and input/output lines remain in their previous state. The core timer may be enabled to allow a
periodic exit from the WAIT mode (see Figure 2-6).
2.3.3
The contents of the RAM are retained at supply voltages as low as 2.0Vdc. This is called the data
retention mode, in which data is maintained but the device is not guaranteed to operate.
For lowest power consumption in data retention mode the device should be put into STOP mode
before reducing the supply voltage, to ensure that all the clocks are stopped. If the device is not in
STOP mode then it is recommended that RESET be held low while the power supply is outside
the normal operating range, to ensure that processing is suspended in an orderly manner.
Recovery from data retention mode, after the power supply has been restored, is by pulling the
RESET line high.
To put the MCU into data retention mode:
•
•
To take the MCU out of data retention:
•
•
MOTOROLA
2-12
Set RESET pin to zero
Reduce the voltage on VDD. RESET must remain low during data retention mode
Return VDD to normal operating level
Return RESET to logical one.
WAIT
Data retention
2
C remains active. An interrupt from the core timer, 16-bit timer or I
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05L28
2
C (if enabled)
TPG
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