CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet - Page 121

• Manufacturer Part Number: CY8C32_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-56955 Rev. *N
Description Title: PSoC
Document Number: 001-56955
*M
*N
3645908
3648803
06/14/2012
06/18/2012
®
3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC
MKEA
MKEA
WKA/
Added paragraph clarifying that to achieve low hibernate current, you must limit
the frequency of IO input signals.
Revised description of IPOR and clarified PRES term.
Changed footnote to state that all GPIO input voltages - not just analog voltages
- must be less than Vddio.
Updated 100-TQFP package drawing
Clarified description of opamp Iout spec
Changed “compliant with I2C” to “compatible with I2C”
Updated 48-QFN package drawing
Changed reset status register description text to clarify that not all reset sources
are in the register
Updated example PCB layout figure
Removed text stating that FTW is a wakeup source
Changed supply ramp rate spec from 1 V/ns to 0.066 V/µs
Added “based on char” footnote to voltage monitors response time spec
Changed analog global spec descriptions and values
Added spec for ESDhbm for when Vssa and Vssd are separate
Added a statement about support for JTAG programmers and file formats
Changed comparator specs and conditions
Added text describing flash cache, and updated related text
Changed text and added figures describing Vddio source and sink
Added a statement about support for JTAG programmers and file formats.
Changed comparator specs and conditions
Added text on adjustability of buzz frequency
Updated terminology for “master” and “system” clock
Deleted the text “debug operations are possible while the device is reset”
Deleted and updated text regarding SIO performance under certain power ramp
conditions
Removed from boost mention of 22 µH inductors. This included deleting some
graph figures.
Changed DAC high and low speed/power mode descriptions and conditions
Changed IMO startup time spec
Added text on XRES and PRES re-arm times
Added text about usage in externally regulated mode
Updated package diagram spec 001-45616 to *D revision.
Changed supply ramp rate spec from 1 V/ns to 0.066 V/µs
Changed text describing SIO modes for overvoltage tolerance
Added chip Idd specs for active and low-power modes, for multiple voltage,
temperature and usage conditions
Added chip Idd specs for active and low-power modes, for multiple voltage,
temperature and usage conditions
Updated del-sig ADC spec tables, to replace three the instances of “16 bit” with
“12 bit”
No changes. EROS update.
PSoC
®
3: CY8C32 Family
®
)
Data Sheet
Page 121 of 122