CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet - Page 50

• Manufacturer Part Number: CY8C32_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

7.7 I
The I
designed to interface the PSoC device with a two wire I
communication bus. The bus is compatible with Philips ‘The I
Specification’ version 2.1. Additional I
instantiated using Universal Digital Blocks (UDBs) in PSoC
Creator, as required.
To eliminate the need for excessive CPU intervention and
overhead, I
and generation of framing bits. I
or multimaster (Slave and Master)
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I
DSI routing and allows direct connections to any GPIO or SIO
pins.
I
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I
two special sets of SIO pins.
Document Number: 001-56955 Rev. *N
2
Note
SDA
SCL
14. Fixed-block I2C does not support undefined bus conditions. These conditions should be avoided, or the UDB-based I2C component should be used instead.
C provides hardware address detect of a 7-bit address without
2
2
C peripheral provides a synchronous two wire interface
C
Condition
START
2
C specific support is provided for status detection
ADDRESS
1 - 7
2
C pin connections are limited to the
2
C operates as a slave, a master,
[14]
R/W
8
. In slave mode, the unit
2
2
C interfaces can be
C interfaces through the
Figure 7-20. I
ACK
9
2
C serial
2
1 - 7
C Complete Transfer Timing
2
DATA
C
I








Data transfers follow the format shown in
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
However, if a master still wishes to communicate on the bus, it
can generate a repeated START condition (Sr) and address
another slave without first generating a STOP condition. Various
combinations of read/write formats are then possible within such
a transfer.
2
C features include:
8
Slave and Master, Transmitter, and Receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
Support for bus speeds up to 1 Mbps
7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support – SMBus
supported in hardware in UDBs)
7-bit hardware address compare
Wake from low-power modes on address match
ACK
9
PSoC
1 - 7
DATA
®
3: CY8C32 Family
8
Figure
ACK
Data Sheet
9
Page 50 of 122
7-20. After the
Condition
STOP