CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet - Page 33

• Manufacturer Part Number: CY8C32_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

The switching frequency can be set to 400 kHz or 32 kHz, to
optimize efficiency and component cost. The 400 kHz frequency
is generated using an oscillator in the boost converter block. The
32 kHz frequency is derived from the 32 kHz external crystal
oscillator (kHzECO) block. The 32 kHz frequency is primarily
intended for boost standby mode.
At 400 kHz VBOOST is limited to 4 × VBAT.
The boost converter can be operated in two different modes:
active and standby. Active mode is the normal mode of operation
where the boost regulator actively generates a regulated output
voltage. In standby mode, most boost functions are disabled,
thus reducing power consumption of the boost circuit. The
converter can be configured to provide low-power, low-current
regulation in the standby mode. The external 32 kHz crystal can
be used to generate inductor boost pulses on the rising and
falling edge of the clock when the output voltage is less than the
programmed value. This is called automatic thump mode (ATM).
The boost typically draws 200 µA in active mode and 12 µA in
standby mode. The boost operating modes must be used in
conjunction with chip power modes to minimize the total chip
power consumption.
available in different chip power modes.
Table 6-4. Chip and Boost Power Modes Compatibility
If the boost converter is not used in a given application, tie the
VBAT, VSSB, and VBOOST pins to ground and leave the Ind pin
unconnected.
6.3 Reset
CY8C32 has multiple internal and external reset sources
available. The reset sources are:


Document Number: 001-56955 Rev. *N
Chip – Active mode
Chip – Sleep mode
Chip – Hibernate mode Boost can only be operated in active
Chip Power Modes
Power source monitoring – The analog and digital power
voltages, VDDA, VDDD, VCCA, and VCCD are monitored in
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
External – The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must
all have voltage applied before the part comes out of reset.
Table 6-4
Boost can be operated in either active
or standby mode.
Boost can be operated in either active
or standby mode. However, it is recom-
mended to operate boost in standby
mode for low-power consumption
mode. However, it is recommended not
to use boost in chip hibernate mode
due to high current consumption in
boost active mode
lists the boost power modes
Boost Power Modes


Figure 6-7. Resets
The term device reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register shows some of the resets or power voltage
monitoring interrupts. The program may examine this register to
detect and report certain exception conditions. This register is
cleared after a power-on reset. For details see the Technical
Reference Manual.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors


Reset
Pin
Watchdog timer – A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
Software – The device can be reset under program control.
IPOR – Initial Power-on Reset
At initial power on, IPOR monitors the power voltages V
V
approximately 1 volt, which is below the lowest specified
operating voltage but high enough for the internal circuits to be
reset and to hold their reset state. The monitor generates a
reset pulse that is at least 150 ns wide. It may be much wider
if one or more of the voltages ramps up slowly.
If after the IPOR triggers either V
trigger point, in a non-monotonic fashion, it must remain below
that point for at least 10 µs. The hysteresis of the IPOR trigger
point is typically 100 mV.
After boot, the IPOR circuit is disabled and voltage supervision
is handed off to the precise low-voltage reset (PRES) circuit.
PRES – Precise Low Voltage Reset
This circuit monitors the outputs of the analog and digital
internal regulators after power up. The regulator outputs are
compared to a precise reference voltage. The response to a
PRES trip is identical to an IPOR reset.
After PRES has been deasserted, at least 10 µs must elapse
before it can be reasserted.
DDA
, V
VDDD VDDA
CCD
Watchdog
Software
Monitors
External
Register
Voltage
Power
Reset
Timer
Reset
Level
and V
PSoC
CCA
. The trip level is not precise. It is set to
Controller
®
Reset
3: CY8C32 Family
DDX
drops back below the
System
Processor
Reset
Interrupt
Data Sheet
Page 33 of 122
DDD
,