CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet - Page 3
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CY8C32_12
Manufacturer Part Number
CY8C32_12
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY8C32_12.pdf
(122 pages)
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1. Architectural Overview
Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC
PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1
family. They are:
Document Number: 001-56955 Rev. *N
0. 5 to 5.5V
( Optional )
32. 7 68 KHz
8051 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
( Optional )
( Optional )
4- 25 MHz
illustrates the major components of the CY8C32
System Wide
Resources
Clocking System
Power Management
Xtal
Osc
IMO
1.8V LDO
POR and
Power
Timer
System
Wake
Sleep
LVD
SMP
WDT
RTC
ILO
and
Digital Interconnect
8- Bit
Timer
I2C Slave
EEPROM
UART
Figure 1-1. Simplified Block Diagram
EMIF
LCD Direct
Temperature
UDB
UDB
UDB
UDB
CapSense
Universal Digital Block Array (24 x UDB)
Sensor
Drive
Quadrature Decoder
Memory System
8- Bit SPI
UDB
UDB
UDB
UDB
FLASH
SRAM
12- Bit SPI
12- Bit PWM
Logic
UDB
UDB
UDB
DAC
UDB
16- Bit
PWM
System Bus
16- Bit PRS
8- Bit
Timer
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the Digital System Interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
Digital System
UDB
UDB
UDB
UDB
Analog Interconnect
Analog subsystem
Logic
Cortex M3
8051 or
Analog System
CPU
UDB
UDB
UDB
UDB
ADC
Del Sig
CPU System
ADC
1 x
UDB
UDB
UDB
UDB
Controller
Interrupt
PHUB
DMA
PSoC
®
) devices, part of a scalable 8-bit
®
CMP
2 x
Program &
Boundary
3: CY8C32 Family
Debug
Program
Debug &
+
FS USB
-
Master /
Trace
Scan
Slave
I2C
2.0
Data Sheet
USB
PHY
Page 3 of 122
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