CY8C32_12 CYPRESS [Cypress Semiconductor], CY8C32_12 Datasheet - Page 7

• Manufacturer Part Number: CY8C32_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-56955 Rev. *N
Notes
9. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
10. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
(Configurable XRES, GPIO) P1[2]
(TCK, SWDCK, GPIO) P1[1]
(TMS, SWDIO, GPIO) P1[0]
(TDO, SWV, GPIO) P1[3]
(I2C0: SDA, SIO) P12[5]
(I2C0: SCL, SIO) P12[4]
(NTRST, GPIO) P1[5]
(TDI, GPIO) P1[4]
(GPIO) P2[6]
(GPIO) P2[7]
VBOOST
VDDIO1
VSSD
XRES
VSSB
VBAT
IND
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
Figure 2-5. 68-pin QFN Part Pinout
Lines show VDDIO
to I/O supply
association
(TOP VIEW)
QFN
[10]
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
PSoC
P0[3] (GPIO, EXTREF0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
VDDIO3
®
3: CY8C32 Family
Data Sheet
Page 7 of 122