CY8C5246LTI-029 CYPRESS [Cypress Semiconductor], CY8C5246LTI-029 Datasheet - Page 50

• Manufacturer Part Number: CY8C5246LTI-029
• Manufacturer: CYPRESS [Cypress Semiconductor]

Note that, while the debug interface at reset is always SWD, any
standard SWD or JTAG debugging tool can switch from SWD to
4-pin JTAG or vice versa without requiring port acquisition, using
a standard sequence defined by ARM.
When using JTAG pins as standard GPIO, make sure that the
GPIO functionality and PCB circuits do not interfere with JTAG
use.
9.3 Debug Features
The CY8C52 supports the following debug features:
9.4 Trace Features
The following trace features are supported:
9.5 SWV and TRACEPORT Interfaces
The SWV and TRACEPORT interfaces provide trace data to a
debug host via the Cypress MiniProg3 or an external trace port
analyzer. The 5 pin TRACEPORT is used for rapid transmission
of large trace streams. The single pin SWV mode is used to
minimize the number of trace pins. SWV is shared with a JTAG
pin. If debugging and tracing are done at the same time then
SWD may be used with either SWV or TRACEPORT, or JTAG
may be used with TRACEPORT, as shown in
Document Number: 001-66236 Rev. **
Halt and single-step the CPU
View and change CPU and peripheral registers, and RAM
addresses
Six program address breakpoints and two literal access
breakpoints
Data watchpoint events to CPU
Patch and remap instruction from flash to SRAM
Debugging at the full speed of the CPU
Debug operations are possible while the device is reset, or in
low power modes
Compatible with PSoC Creator and MiniProg3 programmer and
debugger
Standard JTAG or SWD programming and debugging interface
makes CY8C52 compatible with other popular third-party tools
(for example, ARM / Keil)
Instruction trace
Data watchpoint on access to data address, address range, or
data value
Trace trigger on data watchpoint
Debug exception trigger
Code profiling
Counters for measuring clock cycles, folded instructions,
load/store operations, sleep cycles, cycles per instruction,
interrupt overhead
Interrupt events trace
Software event monitoring, “printf-style” debugging
PRELIMINARY
Table
9-1.
.
Table 9-1. Debug Configurations
9.6 Programming Features
The JTAG or SWD interface provides full programming support.
The entire device can be erased, programmed, and verified.
Designers can increase flash protection levels to protect
firmware IP. Flash protection can only be reset after a full device
erase. Individual flash blocks can be erased, programmed, and
verified, if block security settings permit.
9.7 Device Security
PSoC 5 offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0x50536F43) to a Write Once Latch (WOL). The WOL must be
programmed at V
The Write Once Latch is a type of nonvolatile latch (NVL). The
cell itself is an NVL with additional logic wrapped around it. Each
WOL device contains four bytes (32 bits) of data. The wrapper
outputs a ‘1’ if a super-majority (28 of 32) of its bits match a
pre-determined pattern (0x50536F43); it outputs a ‘0’ if this
majority is not reached. When the output is 1, the Write Once NV
latch locks the part out of Debug and Test modes; it also
permanently gates off the ability to erase or alter the contents of
the latch. Matching all bits is intentionally not required, so that
single (or few) bit failures do not deassert the WOL output. The
state of the NVL bits after wafer processing is truly random with
no tendency toward 1 or 0.
The WOL only locks the part after the correct 32-bit key
(0x50536F43) is loaded into the NVL's volatile memory,
programmed into the NVL's nonvolatile cells, and the part is
reset. The output of the WOL is only sampled on reset and used
to disable the access. This precaution prevents anyone from
reading, erasing, or altering the contents of the internal memory.
You can write the key into the WOL to lock out external access
only if no flash protection is set (see
page 16). However, after setting the values in the WOL, you still
have access to the part until it is reset. Therefore, you can write
the key into the WOL, program the flash protection data, and
then reset the part to lock it.
All debug and trace
disabled
JTAG
SWD
SWV
TRACEPORT
JTAG + TRACEPORT
SWD + SWV
SWD + TRACEPORT
Debug and Trace
PSoC
Configuration
®
5: CY8C52 Family Datasheet
DDD
≤ 3.3 V.
GPIO Pins Used
“Flash Security”
0
4
2
1
5
9
3
7
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