CY8C5246LTI-029 CYPRESS [Cypress Semiconductor], CY8C5246LTI-029 Datasheet - Page 8

• Manufacturer Part Number: CY8C5246LTI-029
• Manufacturer: CYPRESS [Cypress Semiconductor]

3. Pin Descriptions
IDAC0. Low resistance output pin for high IDAC.
Extref0, Extref1. External reference input to the analog system.
GPIO. General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator
pin. If a crystal is not used, then Xi must be shorted to ground
and Xo must be left floating.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
SIO. Special I/O provides interfaces to the CPU, digital
peripherals and interrupts with a programmable high threshold
voltage, analog comparator, high sink current, and high
impedance state when the device is unpowered.
SWDCK. Serial wire debug clock programming and debug port
connection.
SWDIO. Serial wire debug Input and output programming and
debug port connection.
TCK. JTAG Test Clock programming and debug port connection.
TDI. JTAG Test Data In programming and debug port
connection.
TDO. JTAG Test Data Out programming and debug port
connection.
Document Number: 001-66236 Rev. **
Notes
6. GPIOs with opamp outputs are not recommended for use with CapSense.
Figure 2-4. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
[6]
.
Plane
Vssd
PRELIMINARY
Vddd
Vssd
TMS. JTAG Test Mode Select programming and debug port
connection.
TRACECLK. Cortex-M3
TRACEDATA pins.
TRACEDATA[3:0]. Cortex-M3
output data.
SWV. Single wire viewer output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
of from a V
USB.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from V
of from a V
USB.
V
V
V
Requires a 1 µF capacitor to V
external use.
V
The two V
between them as short as possible, and a 1-µF capacitor to
V
external use.
V
regulator. V
device. All other supply pins must be less than or equal to V
BOOST
BAT
CCA
CCD
SSD
DDA
PSoC
Vssa
. Battery supply to boost pump.
; see
. Output of analog core regulator and input to analog core.
. Output of digital core regulator and input to digital core.
. Supply for all analog peripherals and analog core
. Power sense connection to boost pump.
Vdda
DDIO
DDIO
CCD
Power System
DDA
®
. Pins are Do Not Use (DNU) on devices without
. Pins are Do Not Use (DNU) on devices without
5: CY8C52 Family Datasheet
pins must be shorted together, with the trace
must be the highest voltage present on the
Plane
Vssa
on page 21. Regulator output not for
TRACEPORT
SSA
TRACEPORT
. Regulator output not for
connection,
Page 8 of 94
connections,
DDD
DDD
instead
instead
clocks
DDA
[+] Feedback
[+] Feedback
[+] Feedback
.