CY8C5246LTI-029 CYPRESS [Cypress Semiconductor], CY8C5246LTI-029 Datasheet - Page 9

• Manufacturer Part Number: CY8C5246LTI-029
• Manufacturer: CYPRESS [Cypress Semiconductor]

V
V
V
V
V
V
V
and must be less than or equal to V
with V
should be tied to ground (V
XRES. External reset pin. Active low with internal pull-up.
The Cortex-M3 CPU subsystem includes these features:
Document Number: 001-66236 Rev. **
DDD
DDD
SSA
SSB
SSD
DDIO0
DDIO
ARM Cortex-M3 CPU
Programmable nested vectored interrupt controller (NVIC),
tightly integrated with the CPU core
Full-featured debug and trace module, tightly integrated with
the CPU core
Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB
of SRAM
. Ground for all analog peripherals.
. Ground connection for boost pump.
. Ground for all digital logic and I/O pins.
. Supply for all digital peripherals and digital core regulator.
must be less than or equal to V
must be tied to a valid operating voltage (1.71 V to 5.5 V),
DDIO0
, V
DDIO1
SRAM
SRAM
32 KB
32 KB
, V
Interrupt Inputs
DDIO2
, V
JTAG, SWD
DDIO2
Bus
Matrix
Bus
Matrix
or V
, V
DDIO3
DDIO3
Debug Block
AHB Spokes
SSD
(JTAG and
Controller
Vectored
Interrupt
Nested
(NVIC)
SWD)
or V
. Supply for I/O pins. Each
are not used then that V
GPIO
DDA
SSA
DDA
. If the I/O pins associated
).
AHB
I- Bus
.
Figure 4-1. ARM Cortex-M3 Block Diagram
AHB Bridge & Bus Matrix
PRELIMINARY
C-Bus
D-Bus
AHB
Digital
Prog.
Cortex M3 CPU Core
Peripherals
PHUB
AHB
S-Bus
DDIO
Cortex M3 Wrapper
Analog
Prog.
4. CPU
4.1 ARM Cortex-M3 CPU
The CY8C52 family of devices has an ARM Cortex-M3 CPU
core. The Cortex-M3 is a low power 32-bit three-stage pipelined
Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is
intended for deeply embedded applications that require fast
interrupt handling features.
4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
Cache controller
Peripheral HUB (PHUB)
DMA controller
4-GB address space. Predefined address regions for code,
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
PSoC
DMA
Bus
Matrix
Functions
Special
Watchpoint and
Instrumentation
and Breakpoint
Trace Module
Trace (DWT)
Flash Patch
®
(FPB)
(ITM)
Data
5: CY8C52 Family Datasheet
Cache
Trace Module
Interface Unit
Embedded
Trace Port
(TPIU)
(ETM)
256 KB
Flash
Trace Pins:
5 for TRACEPORT or
1 for SWV mode
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