CY8C5246LTI-029 CYPRESS [Cypress Semiconductor], CY8C5246LTI-029 Datasheet - Page 53

• Manufacturer Part Number: CY8C5246LTI-029
• Manufacturer: CYPRESS [Cypress Semiconductor]

11.2 Device Level Specifications
Specifications are valid for –40 °C ≤ T
except where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Document Number: 001-66236 Rev. **
V
V
V
V
V
V
V
I
Parameter
DD
Notes
DDA
DDA
DDD
DDD
DDIO
CCA
CCD
13. The power supplies can be brought up in any sequence however once stable V
14. The V
15. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available in
16. If V
[15]
PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular
system from the device data sheet and component data sheets.
[14]
CCD
DDIO
and V
Analog supply voltage and input to
analog core regulator
Analog supply voltage, analog
regulator bypassed
Digital supply voltage relative to
V
Digital supply voltage, digital
regulator bypassed
I/O supply voltage relative to V
Direct analog core voltage input
(Analog regulator bypass)
Direct digital core voltage input
(Digital regulator bypass)
Active Mode, V
Execute from flash cache, see
Cache Controller
Flash Program Memory
Sleep Mode
CPU = OFF
RTC = ON (= ECO32K ON, in low
power mode)
Sleep timer = ON (= ILO ON at
1 kHz)
WDT = OFF
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input,
unregulated output mode
Comparator = ON
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
POR = ON
Boost = OFF
SIO pins in single ended input,
unregulated output mode
supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ V
SSD
CCA
are externally regulated, the voltage difference between V
[17]
Description
[16]
DD
on page 11 and
= 1.71 V–5.5 V
on page 16
A
≤ 85 °C and T
SSIO
PRELIMINARY
Analog core regulator enabled
Analog core regulator disabled
Digital core regulator enabled
Digital core regulator disabled
Analog core regulator disabled
Digital core regulator disabled
CPU at 6 MHz
V
V
V
V
DD
DD
DD
DD
J
= V
= V
= V
= V
≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
DDIO
DDIO
DDIO
DDIO
= 1.71–1.95 V T= –40 °C
= 4.5–5.5 V
= 2.7–3.6 V
= 2.7–3.6 V
CCD
Conditions
DDA
and V
must be greater than or equal to all other supplies.
PSoC
CCA
must be less than 50 mV.
T = –40 °C
T = 25 °C
T = 85 °C
T= –40 °C
T= 25 °C
T= 85 °C
T= –40 °C
T= 25 °C
T= 85 °C
T= 25 °C
T= 85 °C
T= 25 °C
®
5: CY8C52 Family Datasheet
1.71
1.71
1.71
1.71
1.71
Min
1.8
1.8
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ
1.8
1.8
1.8
1.8
–
–
–
–
2
–
–
–
–
–
2
–
–
–
–
–
V
V
DDA
DDA
Max
1.89
1.89
1.89
1.89
5.5
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 53 of 94
[13]
[13]
DDIO
Units
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
≤ V
DDA
[+] Feedback
[+] Feedback
[+] Feedback
.