MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 173

• Manufacturer Part Number: MC68HC705V12CFN
• Description: The Motorola microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC705V12
MOTOROLA
—
Rev. 3.0
NBFS — Normalization Bit Format Select Bit
TEOD — Transmit End-of-Data Bit
This bit controls the format of the normalization bit (NB). (See
14-19.) SAE J1850 strongly encourages using an active long (logic 0)
for in-frame responses containing cyclical redundancy check (CRC)
and an active short (logic 1) for in-frame responses without CRC.
This bit is set by the programmer to indicate the end of a message is
being sent by the BDLC. It will append an 8-bit CRC after completing
transmission of the current byte. This bit also is used to end an
in-frame response (IFR). If the transmit shadow register is full when
TEOD is set, the CRC byte will be transmitted after the current byte in
the Tx shift register and the byte in the Tx shadow register have been
transmitted. (See
description of the transmit shadow register.) Once TEOD is set, the
transmit data register empty flag (TDRE) in the BDLC state vector
register (BSVR) is cleared to allow lower priority interrupts to occur.
See
Byte Data Link Controller – Digital (BDLC–D)
1 = NB that is received or transmitted is a 0 when the response part
0 = NB that is received or transmitted is a 1 when the response part
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of
14.7.4 BDLC State Vector
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
the first CRC bit that is sent or if an error is detected. When
TEOD is used to end an IFR transmission, TEOD is cleared
when the BDLC receives back a valid EOD symbol or an error
condition occurs.
14.6.3 Rx and Tx Shadow Registers
Byte Data Link Controller – Digital (BDLC–D)
Register.
BDLC CPU Interface
Advance Information
for a
Figure
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