MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 71
MC68HC705V12CFN
Manufacturer Part Number
MC68HC705V12CFN
Description
The Motorola microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC705V12CFN.pdf
(248 pages)
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5.4.2 Computer Operating Properly Reset (COPR)
5.4.2.1 Resetting the COP
5.4.2.2 COP during Wait Mode
5.4.2.3 COP during Stop Mode
MC68HC705V12
MOTOROLA
—
Rev. 3.0
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. Regardless of an internal or external reset,
the MCU comes out of a COP reset according to the pin conditions that
determine mode selection.
The COP reset function is enabled or disabled by the MOR[COPE] bit
and is verified during production testing.
The COP watchdog reset will activate the internal pulldown device
connected to the RESET pin.
Preventing a COP reset is done by writing a 0 to the COPR bit. This
action will reset the counter and begin the timeout period again. The
COPR bit is bit 0 of address $3FF0. A read of address $3FF0 will return
user data programmed at that location.
The COP will continue to operate normally during wait mode. The
system should be configured to pull the device out of wait mode
periodically and reset the COP by writing to the COPR bit to prevent a
COP reset.
When the STOP enable mask option is selected, stop mode disables the
oscillator circuit and thereby turns the clock off for the entire device. The
COP counter will be reset when stop mode is entered. If a reset is used
to exit stop mode, the COP counter will be held in reset during the 4064
cycles of startup delay. If any operable interrupt is used to exit stop
mode, the COP counter will not be reset during the 4064-cycle startup
delay and will have that many cycles already counted when control is
returned to the program.
Resets
Advance Information
Internal Resets
Resets
71
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