FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 136

• Manufacturer Part Number: FDC37B787QF
• Description: Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
• Manufacturer: SMSC [SMSC Corporation]

RTC INTERFACE
The ISA interface is functionally compatible with
the 8042-style host interface. It consists of the D0-
7 data bus, the nIOR, nIOW and the Status
*Bank 0 is at 70h. Bank 1 is relocatable via the RTC Mode Register and the Secondary Base Address for
RTC Bank 1 (CR62 and CR63). See Configuration section.
RTC Address Register
Writing to this register sets the CMOS address
that will be read or written.
RTC Data Register
A read of this register will read the contents of the
selected CMOS register. A write to this register
will write to the selected CMOS register.
REAL TIME CLOCK
The Real Time Clock is a complete time of day
clock with a day of month alarm, calendar (up to
the year 9999), a programmable periodic interrupt,
and a programmable square wave generator.
Features
Counts seconds, minutes, and hours of the day.
Counts days of the week, date, month, year and
century.
Day of Month Wake-Up Alarm
Binary or BCD representation of time, calendar
and alarms.
Three interrupts - each is separately software
maskable. (No daylight savings time)
256 Bytes of CMOS RAM.
Port Definition and Description
ISA ADDRESS*
0x70
0x71
Addresses 0x60, 0x64, 0x70 and 0x71 are qualified by AEN
Base* + 1
Base*
(R/W)
(R/W)
Table 61 - ISA I/O Address Map
RTC Bank 1
RTC Bank 1
BLOCK
RTC
RTC
138
register, Input Data register, and Output Data
register. Table 61 shows how the interface
decodes the control signals.
above
keyboard and mouse IRQs.
OSCILLATOR
Crystal Oscillator input. A 32.768 kHz crystal
connected externally on the XTAL1 and XTAL2
pins generates the 32.768 kHz RTC input clock.
Maximum clock frequency is 32.768 KHz.
RTC Reset
The clock, calendar, or RAM functions are not
affected by the system reset (RESET_DRV
active). When the RESET_DRV pin is active (i.e.,
system reset) and the battery voltage is above 1
volt nominal, the following occurs:
1)
2)
3)
4)
5)
6)
7)
8)
9)
When RESET_DRV is active and the battery
voltage is below 1-volt nominal, the following
occurs:
Address Register
Data Register
Address Register
Data Register
Periodic Interrupt Enable (PIE) is cleared to 0.
Alarm Interrupt Enable (AIE) bit is cleared to
0.
Update Ended Interrupt Enable (UIE) bit is
cleared to 0.
Update Ended Interrupt Flag (UF) bit is
cleared to 0.
cleared to 0.
Periodic Interrupt Flag (PIF) is cleared to 0.
The RTC and CMOS registers are not
accessible.
Alarm Interrupt Flag (AF) is cleared to 0.
nIRQ pin is in high impedance state.
Interrupt Request Status Flag (IRQF) bit is
signals,
FUNCTION
the
host
interface
In addition to the
includes