FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 141

• Manufacturer Part Number: FDC37B787QF
• Description: Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
• Manufacturer: SMSC [SMSC Corporation]

REGISTER B (BH)
SET
When the SET bit is a "0", the update functions
normally by advancing the counts once per
second. When the SET bit is a "1", an update
PIE
The periodic interrupt enable bit is a read/write bit
which allows the periodic-interrupt flag (PF) bit in
Register C to cause the IRQB port to be driven
MSB
SET
b7
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OSCILLATOR
FREQUENCY
32.768 KHz
32.768 KHz
32.768 KHz
32.768 KHz
32.768 KHz
RATE SELECT
PIE
RS2
b6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
AIE
b5
DV2
Table 67 - Periodic Interrupt Rates
REGISTER A BITS
0
0
0
0
1
1
Table 66 - Divider Selection Bits
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DV1
UIE
0
0
1
1
0
1
b4
PERIOD RATE OF
INTERRUPT
1.953125 ms
143
3.90625 ms
3.90625 ms
122.070 μs
244.141 μs
488.281 μs
976.562 μs
DV0
7.8125 ms
7.8125 ms
15.625 ms
31.25 ms
X
X
62.5 ms
0
1
0
1
125 ms
250 ms
500 ms
cycle in progress is aborted and the program may
initialize the time and calendar bytes without an
update occurring in the middle of initialization.
SET is a read/write bit which is not modified by
RESET_DRV or any internal functions.
low. The program writes a "1" to the PIE bit in
order to receive periodic interrupts at the rate
specified by the RS3-RS0 bits in Register A. A
zero in PIE blocks IRQB from being initiated by a
0.0
RES
b3
32.768 KHz TIME BASE
Reset Divider
Reset Divider
Normal Operate
Test
Test
Reset Divider
DM2
b2
MODE
FREQUENCY OF
INTERRUPT
8.192 KHz
4.096 KHz
2.048 KHz
1.024 KHz
256 Hz
128 Hz
512 Hz
256 Hz
128 Hz
64 Hz
32 Hz
16 Hz
8 Hz
4 Hz
2 Hz
24/12
b1
DSE
LSB
b0