ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 169

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.15.7
4921C–AUTO–01/07
Timer/Counter Timing Diagrams
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM
output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when
WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match
between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x
Register at compare match between OCR2x and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk
is therefore shown as a clock enable signal. In asynchronous mode, clk
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set.
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 4-60. Timer/Counter Timing Diagram, no Prescaling
f
OCnxPCPWM
• OCR2A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
value is MAX the OCn pin value is the same as the result of a down-counting compare match.
To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result
of an up-counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the
way up.
(clk
Figure 4-60
TCNTn
TOVn
clk
I/O
clk
/1)
TN
I/O
=
-------------------- -
N
contains timing data for basic Timer/Counter operation. The figure shows the
f
clk_I/O
510
MAX - 1
Figure 4-59 on page 168
MAX
Figure 4-59 on page
Table 4-60 on page
OCnx has a transition from high to low
ATA6602/ATA6603
BOTTOM
168. When the OCR2A
I/O
172). The actual OC2x
should be replaced by
BOTTOM + 1
169
T2
)