ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 291

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.23.7.8
4.23.7.9
4921C–AUTO–01/07
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SELFPRGEN are set in
SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it is rec-
ommended to load the Z-pointer with 0x0001 (same as used for reading the lO
compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock
bits. When programming the Lock bits the entire Flash can be read during the operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set
in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET
and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM
instruction is executed within three CPU cycles or no SPM instruction is executed within four
CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the
Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte
(FLB) will be loaded in the destination register as shown below. Refer to
299
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the BLBSET and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
shown below. Refer to
Fuse High byte.
for a detailed description and mapping of the Fuse Low byte.
Bit
Rd
Bit
Rd
Bit
Rd
FHB7
FLB7
7
–
7
7
Table 4-117 on page 299
FLB6
FHB6
6
–
6
6
BLB12
FHB5
FLB5
5
5
5
BLB11
FHB4
FLB4
4
4
4
for detailed description and mapping of the
BLB02
FHB3
FLB3
3
3
3
ATA6602/ATA6603
BLB01
FHB2
FLB2
2
2
2
FLB1
FHB1
LB2
1
1
1
Table 4-116 on page
ck
FHB0
FLB0
bits). For future
LB1
0
0
0
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