ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 278

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.21.6.4
4.21.6.5
278
ATA6602/ATA6603
ADC Control and Status Register B – ADCSRB
Digital Input Disable Register 0 – DIDR0
Table 4-101. ADC Auto Trigger Source Selections
• Bit 7, 5:3 – Res: Reserved Bits
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
• Bits 7:6 – Res: Reserved Bits
• Bit 5..0 – ADC5D..ADC0D: ADC5..0 Digital Input Disable
Read/Write
Initial Value
Initial Value
Read/Write
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when ADCSRB is written.
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trig-
ger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A
conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that
switching from a trigger source that is cleared to a trigger source that is set, will generate a
positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion.
Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the
ADC Interrupt Flag is set
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when DIDR0 is written.
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set.
When an analog signal is applied to the ADC5..0 pin and the digital input from this pin is not
needed, this bit should be written logic one to reduce power consumption in the digital input
buffer.
Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do not
require Digital Input Disable bits.
Bit
Bit
ADTS2
0
0
0
0
1
1
1
1
R
R
7
–
0
7
–
0
ACME
ADTS1
R/W
R
6
–
0
6
0
0
0
1
1
0
0
1
1
.
ADC5D
R/W
R
5
0
5
–
0
ADC4D
R/W
ADTS0
R
4
0
4
–
0
0
1
0
1
0
1
0
1
ADC3D
R/W
R
3
–
0
3
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
ADC2D
ADTS2
R/W
R/W
2
0
2
0
ADC1D
ADTS1
R/W
R/W
1
0
1
0
ADTS0
ADC0D
R/W
R/W
0
0
0
0
4921C–AUTO–01/07
ADCSRB
DIDR0