ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 75

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.8.9.1
4921C–AUTO–01/07
Watchdog Timer Control Register - WDTCSR
Table 4-24.
• Bit 7 - WDIF: Watchdog Interrupt Flag
• Bit 6 - WDIE: Watchdog Interrupt Enable
• Bit 4 - WDCE: Watchdog Change Enable
• Bit 3 - WDE: Watchdog System Reset Enable
Initial Value
Read/Write
WDTON
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is
configured for interrupt. WDIF is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag.
When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Inter-
rupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in
Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog
Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out
in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear
WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode).
This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in
Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should how-
ever not be done within the interrupt service routine itself, as this might compromise the
safety-function of the Watchdog System Reset mode. If the interrupt is not executed before
the next time-out, a System Reset will be applied.
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE
bit, and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF
is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets dur-
ing conditions causing failure, and a safe start-up after the failure.
Bit
0
0
0
0
1
Watchdog Timer Configuration
WDIF
R/W
WDE
7
0
0
0
1
1
x
WDIE
R/W
6
0
WDIE
0
1
0
1
x
WDP3
R/W
5
0
Mode
Stopped
Interrupt Mode
System Reset Mode
Interrupt and System Reset
Mode
System Reset Mode
WDCE
R/W
4
0
WDE
R/W
X
3
ATA6602/ATA6603
WDP2
R/W
2
0
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to System
Reset Mode
Reset
WDP1
R/W
1
0
WDP0
R/W
0
0
WDTCSR
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