PSF21150 INFINEON [Infineon Technologies AG], PSF21150 Datasheet - Page 176

• Manufacturer Part Number: PSF21150
• Description: IPAC-X ISDN PC ADAPTER CIRCUIT
• Manufacturer: INFINEON [Infineon Technologies AG]

4.1.6
Value after reset: 00
CMDRD
RMC ... Receive Message Complete
Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By
setting this bit, the microcontroller confirms that it has fetched the data, and indicates that
the corresponding space in the RFIFOD may be released.
RRES ... Receiver Reset
HDLC receiver is reset, the RFIFOD is cleared of any data.
STI ... Start Timer 1
The IPAC-X timer 1 is started when STI is set to one. The timer is stopped by writing to
the TIMR1 register.
Note: Timer 2 is controlled by the TIMR2 register only.
XTF ... Transmit Transparent Frame
After having written up to 16 or 32 bytes (EXMD1.XFBS) to the XFIFOD, the
microcontroller initiates the transmission of a transparent frame by setting this bit to ’1’.
The opening flag is automatically added to the message by the IPAC-X (except in the
extended transparent mode where no flags are used).
XME ... Transmit Message End
By setting this bit to ’1’ the microcontroller indicates that the data block written last to the
XFIFOD completes the corresponding frame. The IPAC-X terminates the transmission
by appending the CRC (if EXMD1.XCRC=0) and the closing flag sequence to the data
(except in the extended transparent mode where no such framing is used).
XRES ... Transmitter Reset
The D-channel HDLC transmitter is reset and the XFIFOD is cleared of any data. This
command can be used by the microcontroller to abort a frame currently in transmission.
Note: After an XPR interrupt further data has to be written to the XFIFOD and the
Data Sheet
appropriate Transmit Command (XTF) has to be written to the CMDRD register
again to continue transmission, when the current frame is not yet complete (see
7
CMDRD - Command Register D-channel
RMC RRES
H
0
STI
176
XTF
0
Detailed Register Description
XME XRES
0
PSB 21150
PSF 21150
2000-07-21
WR (21)