PSF21150 INFINEON [Infineon Technologies AG], PSF21150 Datasheet - Page 69

• Manufacturer Part Number: PSF21150
• Description: IPAC-X ISDN PC ADAPTER CIRCUIT
• Manufacturer: INFINEON [Infineon Technologies AG]

3.4
Figure 36
7.68 MHz clock signal (f
(8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames.
In LT modes these pins are input and in LT-T mode an 1536 kHz clock synchronous to
S is output at SCLK which can be used for DCL input.
An internal clock divider provides an FSC (ACFG2.FBS=0) or BCL (ACFG2.FBS=1)
output on pin AUX5/FBOUT derived from the DCL clock. The output can be enabled via
ACFG2.A5SEL=1.
The FSC signal is used to generate the pulse lengths of the different reset sources C/I
Code, EAW pin and Watchdog (see
Figure 36
Data Sheet
XTAL
7.68 MHz
shows the clock system of the IPAC-X. The oscillator is used to generate a
Clock Generation
OSC
Clock System of the IPAC-X
f
XTAL
XTAL
DPLL
). In TE mode the DPLL generates the IOM-2 clocks FSC
Chapter
Reset
Generation
SW Reset
C/I
EAW
Watchdog
ACFG2.FBS
69
3.2.4).
ACFG2.A5SEL
Description of Functional Blocks
FSC (TE mode)
DCL (TE mode)
BCL (TE mode)
SCLK (LT-T mode)
125 µs t 250 µs
125 µs t 250 µs
125 µs t 250 µs
125 µs t 250 µs
FBOUT (FSC/BCL output)
PSB 21150
PSF 21150
2000-07-21
21150_06